Anderson Pires Singulani

Through Silicon Via Reliability

Vertical integration of diverse semiconductor technologies can be achieved by utilizing interconnections through entire silicon substrates, known as through silicon vias (TSVs). TSVs present an interesting case study for reliability evaluation, given the particular fabrication technologies, geometries, and potential failure modes associated with such structures. A specific TSV technology is introduced, and key parameters for reliability assessment, such as residual stress, resistance, leakage, and dielectric breakdown, are discussed. Reliability data are presented, including the characterization of TSV parameters as a function of various accelerated lifetime stress tests, as well as assessments of the density and impact of TSV manufacturing defects. The presented data demonstrate that while the TSV is inherently quite robust, latent manufacturing defects pose a significant risk to long-term reliability. Screening methodologies, defect modes, failure analysis methods, process improvement, and correspondingly improved defect density results are discussed. The results are considered pertinent to the development and reliability of novel 3-D integrated process technologies.

Effects of Bosch scallops on metal layer stress of an open Through Silicon Via technology

Through Silicon Via (TSV) is a lead topic in interconnects and 3D integration research, mainly due to numerous anticipated advantages. However, several challenges must still be overcome if large scale production is to be achieved. In this work, we have studied effects of Bosch scallops concerning mechanical reliability for a specific TSV technology. The presence of scallops on the TSV wall modifies the stress distribution along the via. By means of Finite Element Method (FEM) simulations, we could assess this change and understand the process. The achieved results support experiments and give a better insight into the influence of scallops on the stress in an open TSV.

Thermo-mechanical simulations of an open tungsten TSV

A specific open Through Silicon Via (TSV) technology is analyzed by means of thermo-mechanical Finite Element Method (FEM) simulations in order to assess stress behavior and to identify critical stress points in the structure. An analytical expression is introduced for the stress field around one TSV and its application in the description of the stress in a particular arrangement of vias is discussed. The analysis provides a consistent justification for the robustness of the technology, while it also points out the potential failure points.

Intrinsic stress analysis of tungsten-lined open TSVs

Abstract The effects of silicon etching and subsequent metallization during the fabrication of tungsten-lined open TSVs are examined using a combination of measurements and simulations. The total stress through a tungsten film deposited on a flat wafer is measured and finite element simulations are performed in order to identify the intrinsic and thermal stress components in the film. The data is then used to observe and model the stress through a TSV structure, which is etched using the DRIE process, resulting in scalloped inner sidewalls through the TSV opening. The scalloped structure is then compared to the ideal flat alternative with regard to the stress through the metal film and the TSVs electrical parameters, including resistance, capacitance, and inductance. It is found that the stress around the scallop varies significantly while the average stress through the tungsten in the flat TSV is only slightly higher than the stress observed through the scalloped structure. The resistance, capacitance, and inductance are all found to increase in the presence of scallops.

Stress evolution in the metal layers of TSVs with Bosch scallops

We have studied the stress evolution in the tungsten film of a particular open TSV technology during the thermal processing cycle. The film is attached to the via’s wall, where scallops were observed as a result of the Bosch processing. Our work describes a scheme which considers the scallops on the TSV and conjugates a stress model for thin-films with the traditional mechanical FEM approach. The results reveal potential reliability issues and a specific evolution of the stress in the tungsten layer.

Effects of sidewall scallops on open tungsten TSVs

In order to examine the effects of sidewall scallops on through-silicon via (TSV) performance, the etch processes required to generate several TSV geometries are simulated and the resulting structures are imported into a finite element tool for electrical parameter extraction and reliability analysis. The electrical models, which were confirmed using experimental measurements with non-scalloped structures, are applied to the simulated TSV devices. The effects of the scalloped features are investigated by comparing the performance of a TSV with scalloped sidewalls to one with flat walls. In addition, the variation in TSV performance, when the sidewall scallop height is varied, is analyzed. A link between increased scallop height and increased resistance and signal loss is observed. The maximum thermo-mechanical stress in the structure is also noted to increase with the presence of large scallops, but the overall average stress does not vary significantly.

Impact of across-wafer variation on the electrical performance of TSVs

A simulation methodology is presented by which measured equipment variation during silicon DRIE is quantified and the effective variation in the electrical performance of the final TSV devices is found. Using the level set method, process simulations are performed in order to generate structures representative of the equipment variation. The across-wafer variation of the resulting scallop geometry is about 20%, while the electrical performance, including the resistance, capacitance, and inductance of the devices was found to not vary beyond 1%.

Stress evolution on tungsten thin-film of an open through silicon via technology

We have studied the stress evolution in the tungsten film of a particular open TSV technology during the thermal processing cycle. The film is attached to the vias wall and some plasticity is expected in the metal due to the temperature variation. Our work introduces a stress model for thin-films utilizing the traditional mechanical FEM approach. The results reveal potential reliability issues and a specific evolution of the stress in the tungsten layer.

Optical sensor process variability in a 0.18 μm high voltage CMOS technology

We describe an analysis of the main process parameters variability involved in electrical and optical output characteristics of an optical sensor integrating a standard silicon-based NWell in p-epitaxial substrate photodiode and an UV/IR blocking interference filter. This study is done with TCAD simulation following a standard 0.18 μm high voltage CMOS technology fabrication process. The TCAD simulations combined with specific Design of Experiments permit a better understanding of the main electrical and optical responses variabilities of the optical sensor. This results in an improvement of the inline process control parameters and a better modeling of the sensor for future circuit designs integrating this sensor.

Stress Evolution During Nanoindentation in Open TSVs

We applied a nanoindentation technique in an open through silicon via structure by means of simulations. During nanoindentation, a spherical diamond indenter penetrates into the device by applying a force. This penetration causes displacement and deformation of the materials. The simulation results were compared with experimental data, as loading force versus penetration depth. Consequently, we estimated the areas in the structure, in which a mechanical failure due to an external load can be expected. Our simulations revealed the regions with the highest concentration of mechanical stress. These are the critical areas in which the probability of device failure, such as cracking or delamination, is at its highest.