L. Knoll

Inverters With Strained Si Nanowire Complementary Tunnel Field-Effect Transistors

Inverters based on uniaxially tensile strained Si (sSi) nanowire (NW) tunneling field-effect transistors (TFETs) are fabricated. Tilted dopant implantation using the gate as a shadow mask allows self-aligned formation of p-i-n TFETs. The steep junctions formed by dopant segregation at low temperatures improve the band-to-band tunneling, resulting in higher on-currents of n- and p-TFETs of > 10 μA/μm at VDS=0.5 V. The subthreshold slope for n-channel TFETs reaches a minimum value of 30 mV/dec, and is <; 60 mV/dec over one order of magnitude of drain current. The first sSi NW complementary TFET inverters show sharp transitions and fairly high static gain even at very lowVDD=0.2 V. The first transient response analysis of the inverters shows clear output voltage overshoots and a fall time of 2 ns at VDD=1.0 V.

Demonstration of improved transient response of inverters with steep slope strained Si NW TFETs by reduction of TAT with pulsed I-V and NW scaling

We present gate all around strained Si (sSi) nanowire array TFETs with high I_ON (64μA/μm at V_DD=1.0V). Pulsed I-V measurements provide small SS and record I₆₀ of 1×10^-2μA/μm at 300K due to the suppression of trap assisted tunneling (TAT). Scaling the nanowires to 10 nm diameter greatly suppresses the impact of TAT and improves SS and I_ON. Transient analysis of complementary TFET inverters demonstrates experimentally for the first time that device scaling and improved electrostatics yields to faster time response.

Ultrathin Ni Silicides With Low Contact Resistance on Strained and Unstrained Silicon

Ultrathin Ni silicides were formed on silicon-on-insulator (SOI) and biaxially tensile strained SOI (SSOI) substrates. The Ni layer thickness crucially determines the silicide phase formation: With a 3-nm Ni layer, high-quality epitaxial NiSi2 layers were grown at temperatures > 450°C, while NiSi was formed with a 5-nm-thick Ni layer. A very thin Pt interlayer, to incorporate Pt into NiSi, improves the thermal stability and the interface roughness and lowers the contact resistivity. The contact resistivity of epitaxial NiSi2 is about one order of magnitude lower than that of a NiSi layer on both As- and B-doped SOI and SSOI.

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Guided by the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ID = 64 μA/μm at VDS = VGS - Voff = -1.0 V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at VDD as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Electrical characterization of strained and unstrained silicon nanowires with nickel silicide contacts

We present electrical characterization of nickel monosilicide (NiSi) contacts formed on strained and unstrained silicon nanowires (NWs), which were fabricated by top-down processing of initially As(+) implanted and activated strained and unstrained silicon-on-insulator (SOI) substrates. The resistivity of doped Si NWs and the contact resistivity of the NiSi to Si NW contacts are studied as functions of the As(+) ion implantation dose and the cross-sectional area of the wires. Strained silicon NWs show lower resistivity for all doping concentrations due to their enhanced electron mobility compared to the unstrained case. An increase in resistivity with decreasing cross section of the NWs was observed for all implantation doses. This is ascribed to the occurrence of dopant deactivation. Comparing the silicidation of uniaxially tensile strained and unstrained Si NWs shows no difference in silicidation speed and in contact resistivity between NiSi/Si NW. Contact resistivities as low as 1.2 x 10(-8) Omega cm(-2) were obtained for NiSi contacts to both strained and unstrained Si NWs. Compared to planar contacts, the NiSi/Si NW contact resistivity is two orders of magnitude lower.

Simulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI: Impact of Barrier Lowering

In this paper, we develop a procedure to include in device simulators the barrier lowering (BL) effects that appear in the drain and source contacts of Schottky barrier MOSFETs (SB-MOSFETs). We have checked it reproducing experimental results of 20-nm gate-length SB-MOSFETs with NiSi and epitaxial NiSi2 S/D contacts. We make use of the Wentzel-Kramers-Brillouin (WKB) approximation to get the tunneling probabilities through the lowered barriers along with an appropriate calibration of the effective masses which compensates to a large extent the lack of accuracy of the WKB model when diverting from the “wide barrier” assumption. A vertical discretization of the channel is also included to allow the barrier height dependence on the depth inside the channel. We show that corrected simulations including this effect describe in a very accurate way the behavior of these devices. We also check that the striking experimental observation of tunneling current reduction at very short gate lengths is also obtained, in contrast to the scaling behavior of conventional MOSFETs. We successfully explain this fact invoking the modification of the potential inside the channel, i.e., the overlapping of source and drain potential profiles leads to an increase of its total value even though BL mechanisms tend to decrease it in the vicinity of the contacts.

Hole Transport in Strained

Hole velocity and mobility are extracted from quantum-well (QW) biaxially strained Si_0.5Ge_0.5 channel metal-oxide-semiconductor field-effect transistors (MOSFETs) on silicon-on-insulator wafers. Devices have been fabricated at sub-100-nm gate length with HfO₂/TiN gate stacks. A significant hole mobility enhancement over the strained Si mobility curve is observed for QW MOSFETs. We also discuss the relationship between velocity and mobility of the strained SiGe channels with high Ge content for 〈100〉 and 〈110〉 crystal directions. Whereas the mobility increases by 18% for 〈100〉 with respect to 〈110〉, it translates into a modest 8% velocity increase.

\hbox{Si}_{0.5} \hbox{Ge}_{0.5}

We present experimental data on analog device performance of p-type planar and gate all around (GAA) nanowire (NW) Tunnel-FETs (TFETs). 10 nm diameter GAA-NW-TFETs reach a maximum transconductance efficiency of 12.7V-1 which is close to values obtained from simulations. A significant improvement of the analog performance by enhancing the electrostatics from planar TFETs to GAA-NW-TFETs with diameter of 20 nm and 10 nm is demonstrated. A maximum transconductance of 122 μS/μm and on-current up to 23 μ A/μm at a gate overdrive of Vgt = Vd = -1 V were achieved for the GAA-NW-TFETs. Furthermore a good output current-saturation is observed leading to high intrinsic gain up to 217 which is even higher than in 20 nm FinFETs.

QW-MOSFETs With

MOSFETs and Tunnel-FETs (TFETs) based on arrays of nanowires (NWs) with 10 × 10 nm2 cross-section have been fabricated with strained silicon on insulator substrates. MOSFET devices show near ideal subthreshold slope close to 60 mV/dec proving excellent channel control achieved by high-k/metal gate stack. As expected fundamental differences between MOSFETs and TFETs in current-voltage characteristics are observed and analyzed. Low frequency noise spectra are studied for both types of devices. The devices show different behavior in terms of noise spectral density as a function of the applied gate voltage. A Hooge parameter of α = 7.3 × 10-3 is derived for the NW MOSFETs.

\langle\hbox{110}\rangle

We present a method to form ultrathin highly uniform Ni(Al) germanosilicide layers on compressively strained Si1−xGex substrates and their structural characteristics. The uniform Ni(Al) germanosilicide film is formed with Ni/Al alloy at an optimized temperature of 400 °C with an optimized Al atomic content of 20 at. %. We find only two kinds of grains in the layer. Both grains show orthogonal relationship with modified B8 type phase. The growth plane is identified to be {10-10}-type plane. After germanosilicidation the strain in the rest Si1−xGex layer is conserved, which provides a great advantage for device application.