Sebastian Blaeser

Strained Si and SiGe Nanowire Tunnel FETs for Logic and Analog Applications

Guided by the Wentzel-Kramers-Brillouin approximation for band-to-band tunneling (BTBT), various performance boosters for Si TFETs are presented and experimentally verified. Along this line, improvements achieved by the implementation of uniaxial strain in nanowires (NW), the benefits of high-k/metal gates, and newly engineered tunneling junctions as well as the effect of scaling the NW to diameters of 10 nm are demonstrated. Specifically, self-aligned ion implantation into the source/drain silicide and dopant segregation has been exploited to achieve steep tunneling junctions with less defects. The obtained devices deliver high on-currents, e.g., gate-all-around (GAA) NW p-TFETs with 10 nm diameter show ID = 64 μA/μm at VDS = VGS - Voff = -1.0 V, and good inverse subthreshold slopes (SS). Tri-gate TFETs reach minimum SS of 30 mV/dec. Dopant segregation helps to minimize the defect density in the junction and thus trap assisted tunneling (TAT) is reduced. Pulsed current-voltage (I-V) measurements have been used to investigate TAT. We could show that scaled NW devices with multigates are less vulnerable to TAT compared to planar devices due to a shorter tunneling path enabled by the inherently good electrostatics. Furthermore, SiGe NW homo- and heterojunction TFETs have been investigated. The advantages of a SiGe/Si heterostructure as compared to a homojunction device are revealed and the effect of line tunneling which results in an increased BTBT generation is demonstrated. It is also shown that complementary strained Si TFET inverters and p-TFET NAND gates can be operated at VDD as low as 0.2 V. This suggests a great potential of TFETs for ultralow power applications. The analysis of GAA NW TFETs for analog applications provided a high transconductance efficiency and large intrinsic gain, even higher than for state-of-the-art 20 nm FinFETs at low voltages.

Negative differential resistance in direct bandgap GeSn p-i-n structures

Certain GeSn alloys are group IV direct bandgap semiconductors with prospects for electrical and optoelectronical applications. In this letter, we report on the temperature dependence of the electrical characteristics of high Sn-content Ge0.89Sn0.11 p-i-n diodes. NiGeSn contacts were used to minimize the access resistance and ensure compatibility with silicon technology. The major emphasis is placed on the negative differential resistance in which peak to valley current ratios up to 2.3 were obtained. TCAD simulations were performed to identify the origin of the various current contributions, providing evidence for direct band to band tunneling and trap assisted tunneling.

Novel SiGe/Si line tunneling TFET with high Ion at low Vdd and constant SS

This paper presents a novel SiGe/Si tunneling field-effect transistor (TFET) which exploits line tunneling parallel with the gate electric field. The device makes use of selective and self-adjusted silicidation and a counter doped pocket within the SiGe layer at the source tunnel junction, resulting in a high on-current Ion = 6.7 μA/μm at a supply voltage VDD = -0.5 V and a constant subthreshold swing (SS) of about 80 mV/dec over four orders of magnitude of drain-current Id.

SiGe on SOI nanowire array TFETs with homo- and heterostructure tunnel junctions

This paper presents experimental results on tunneling field-effect transistors (TFETs) based on SiGe on SOI nanowire arrays. A SiGe-Si heterostructure TFET with a vertical tunneling junction consisting of an in situ doped SiGe source and a Si channel is demonstrated. The device shows switching behavior over a drain current range of up to 8 orders of magnitude with a minimum slope of 90 mV/dec. A larger tunneling area results in an increase of on-current. The heterojunction TFET shows great improvement compared to a homojunction SiGe on SOI nanowire design with implanted junctions. Temperature dependent measurements and device simulations are performed in order to analyze the tunnel transport mechanism in the devices.

Line Tunneling Dominating Charge Transport in SiGe/Si Heterostructure TFETs

This paper provides an experimental proof that both the ON-current ION and the subthreshold swing SS of Si(Ge)-based tunneling FETs (TFETs) drastically benefit from device architectures promoting line tunneling aligned with the gate electrical field. A novel SiGe/Si heterostructure TFET is fabricated, making use of a selective and self-adjusted silicidation, thus enlarging the area for band-to-band-tunneling (BTBT) in a region directly underneath the gate. In addition, a counter-doped pocket within the SiGe layer at the source tunnel junction is introduced in order to sharpen the corresponding doping profile and, consequently, to shorten the resulting tunneling length. Experimental analysis of activation energies Eα identifies BTBT, dominating the drain current Id in the SiGe/Si heterostructure TFET over a wide region of the gate voltage Vg, thus reducing parasitic influence of Shockley-Read-Hall recombination and trap-assisted tunneling. Both a relatively high ION = 6.7 μA/μm at a supply voltage VDD = 0.5 V and an average SS of about 80 mV/decade over four orders of magnitude of Id were achieved.

Si based tunnel field effect transistors: Recent achievements

Recent achievements of silicon based tunnel field effect transistors (TFETs) and remaining major challenges are overviewed. Particular emphasis is placed on the band to band tunneling (BTBT) junctions, the heart of the device. Dopant segregation from ion implanted ultrathin silicide contacts proved as viable method to achieve steep tunneling junctions. This avoids defect generation by direct implantation into the junction and thus minimizes the risk of trap assisted tunneling. The method was applied to strained silicon, specifically to nanowire array transistors. This enabled the realization of TFETs with fairly high currents and first complementary TFET inverters with sharp transitions and good static gain, even at very low drain voltages of VDD = 0.2 V. These achievements suggest a considerable potential of TFETs for ultralow power applications. Some novel concepts, e.g. to enlarge the tunneling area by “line tunneling”, are addressed. A benchmarking figure summarizes the present status.

Experimental demonstration of planar SiGe on Si TFETs with counter doped pocket

This paper presents both experimental and TCAD simulation results on a planar tunneling field-effect transistor (TFET) using compressively strained Si0.45Ge0.55 on Si. Introducing a counter doped pocket at the source tunnel junction in combination with a selective and self-adjusted silicidation to enlarge the tunneling area enables line tunneling aligned with the gate electric field which results in an enhanced band-to-band tunneling (BTBT) probability, increased on-current Ion and reduced inverse subthreshold swing (SS).

Si based tunneling field effect transistors and inverters

Reducing the drain voltage, VDD, is the key leverage to lower power dissipation in circuits, since the dynamic losses increase proportional to VDD2 multiplied by the frequency. Presently, fully depleted silicon on insulator (FDSOI) technology sets the level pole for ultra-low power applications: At 0.6 V a clock frequency of 1 GHz has been achieved [1]. A further reduction of VDD limits the performance considerably. IMEC announced an ultralow power chip working at voltages from 1V down to 0.4 V. In the sub-threshold regime at 0.4 V the clock frequency reduces to 1 MHz but also the energy consumption drops to a fraction of standard circuits [2]. Numerous applications are foreseeable for battery-powered and energy scavenging smart devices. The question is will tunnel field effect transistors (TFET) provide superior performance.

Strained Si nanowire tunnel FETs and inverters

Steep slope devices, like Tunnel FETs (TFETs), provide small subthreshold slope (SS) <;60mV/dec at 300K and low Ioff, enabling low consumptions of both dynamic and static power. Simulations of TFETs show higher (x8) performance at VDD ~ 0.3 V than MOSFETs at the same standby power and switching energy [1].