L. Ratti

Submicron CMOS technologies for low-noise analog front-end circuits

This paper presents a study of the noise behavior of submicron CMOS transistors, in view of applications to high-density mixed-signal front-end systems for high-granularity detectors. The goal of this work is extending the knowledge in this field, presently focused on 0.25 /spl mu/m processes, to the following generation of CMOS technologies (with 0.18 /spl mu/m minimum gate length). The white component of the noise voltage spectrum, which is most important for fast signal processing, and the 1/f noise contribution are experimentally characterized with noise measurements in a wide frequency range. The results of this analysis are used to establish low-noise design criteria concerning the choice of the polarity and of the channel dimensions (length and width) of the preamplifier input device in low-power operating conditions. A comparison with similar noise measurements on CMOS devices belonging to a 0.35 /spl mu/m process allows estimating the impact of gate-length scaling on both white and 1/f noise components. The noise radiation tolerance is also a key parameter for many front-end systems. It was evaluated by exposing the devices to high doses of ionizing radiation.

Comparison of ionizing radiation effects in 0.18 and 0.25 /spl mu/m CMOS technologies for analog applications

We present a comparative study of ionizing radiation effects in 0.18 and 0.25 /spl mu/m CMOS transistors, with the goal of evaluating the impact of device scaling in the design of low-noise rad-hard analog circuits. Device parameters were monitored before and after irradiation with 10 keV X-rays and /sup 60/Co /spl gamma/-rays and after subsequent annealing. The effects of different biasing conditions during irradiation and annealing are discussed. The results are used to point out the different radiation hardness properties of the examined technologies, belonging to different CMOS generations.

Resolution Limits in 130 nm and 90 nm CMOS Technologies for Analog Front-End Applications

In the last few years CMOS commercial technologies of the quarter micron node have been extensively used in the design of the readout electronics for highly granular detection systems in the particle physics environment. IC designers are now moving to 130 nm CMOS technologies, or even to the next technology generation, to implement readout integrated circuits for future HEP applications. In order to evaluate how scaling down of the device features affects their performances, continuous technology monitoring is mandatory. In this work the results of signal and noise measurements carried out on two CMOS commercial processes are presented. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends and can be used to evaluate the resolution limits achievable for low-noise charge sensitive amplifiers in the 100-nm minimum feature size range.

Proposal of a data sparsification unit for a mixed-mode MAPS detector

The Italian silicon-detectors-with-low-interaction-with material collaboration (SLIM5) has designed, fabricated and tested several prototypes of CMOS monolithic active pixel sensors (MAPS). This paper shows the design of a new mixed-mode chip prototype composed of a bidimensional matrix of pixels, and of an off-pixel digital readout sparsification circuit. The readout logic is based on commercial standard cells and implements an optimized non token readout technique. Also, a MAPS emulator software toool is presented. The project is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments. The readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.

A fabrication process for silicon microstrip detectors with integrated front-end electronics

We report on an research and development activity aimed at the fabrication of silicon microstrip detectors with integrated front-end electronics to be used in high-energy physics and space experiments and medical/industrial imaging applications. A specially tailored fabrication technology has been developed at ITC-IRST (Trento, Italy), which allows for the production of single-sided microstrip detectors, with integrated coupling capacitors and polysilicon resistors, as well as active devices, including N-channel junction field effect transistors and N- or P-channel MOS transistors. The main characteristics of the fabrication process are outlined. Experimental results from the electrical characterization of the devices are reported, showing that transistors with good electrical figures can be obtained within the proposed technology while preserving the basic detector parameters.

JFET front-end circuits integrated in a detector-grade silicon substrate

This paper presents the design and experimental results relevant to front-end circuits integrated on detector-grade high resistivity silicon. The fabrication technology is made available by the Istituto per la Ricerca Scientifica e Tecnologica (ITC-IRST), Trento, Italy and allows using a common substrate for different kinds of active devices, such as N-channel JFETs and MOSFETs, and for pixel, microstrip, and PIN detectors. This research activity is being carried out in the framework of a project aiming at the fabrication of a multichannel mixed analog-digital chip for the readout of solid-state detectors integrated in the same substrate. Possible applications are in the field of medical and industrial imaging and space and high energy physics experiments. An all-JFET charge sensitive amplifier, which can use either a resistive or a nonresistive feedback network, has been characterized. The two configurations have been compared to each other, paying particular attention to noise performances, in view of the design of the complete readout channel. Operation capability in harsh radiation environment has been evaluated through exposure to /spl gamma/-rays from a /sup 60/Co source.

Noise degradation induced by /spl gamma/-rays on P- and N-channel junction field-effect transistors

This paper compares the effects of /spl gamma/-rays on the noise behaviour of P- and N-channel JFETs intended as front-end elements in radiation detector preamplifiers. It will be shown that exposure to /spl gamma/-rays affects the noise spectral density in a way which is substantially different for the two types of devices. As a result of the noise analysis it is suggested that in preamplifiers exposed to /spl gamma/-rays the P-channel JFET should be preferred at processing times in the 1-to-10 /spl mu/s range, while the N-channel device remains superior in applications involving processing times below 0.1 /spl mu/s.

Response of SOI bipolar transistors exposed to /spl gamma/-rays under different dose rate and bias conditions

This work is devoted to the analysis of /spl gamma/-ray effects on the behavior of bipolar junction transistors belonging to a silicon on insulator technology. Such a process is currently being investigated in order to assess its suitability for use in radiation-resistant applications, namely in the design of readout electronics for radiation detectors in high energy physics experiments and for operation in the space environment. Possible sensitivity to low dose-rate was tested by exposing the devices to /spl gamma/-ray sources with different activities. High dose rate irradiations were performed with the devices biased in different operating regions in order to evaluate the effects of bias conditions on the device sensitivity to radiation.

Selection criteria for P- and N-channel JFETs as input elements in low-noise radiation-hard charge preamplifiers

This paper describes a quantitative method for the selection of P- and N-channel junction field-effect transistors as input elements in low-noise charge-sensitive preamplifiers for applications requiring high radiation tolerance. The method is based upon a thorough analysis of ionizing radiation effects on the noise spectral density of such devices. It can be used to predict whether a P- or an N-type transistor is preferable as the front-end element of a preamplifier once the radiation doses and the electronic system readout times are known. Such criteria can he useful in the design of low-noise radiation-resistant electronics suitable for applications where high levels of total radiation dose are expected during the circuit lifetime.

Triple Well CMOS Active Pixel Sensor with In-Pixel Full Signal Analog

We report on a new approach in the design of CMOS monolithic active pixel sensor (MAPS). We realized a first MAPS prototype chip implementing at the pixel level the standard processing chain commonly used for capacitive detectors. The in-pixel signal processing channel includes a low noise charge preamplifier, a shaper, a discriminator and a latch. This readout approach, realized exploiting the triple well option available in the 0.13 mum process by STMicrolectronics, is compatible with already available architectures performing data sparsification at the pixel level. This feature will be implemented in future development of our device to improve the readout speed potential of these sensors with respect to existing MAPS. Using a charge preamplifier to perform charge to voltage conversion, we also extended the area of the sensing electrode to increase the signal collected by a single pixel. The first prototype chips have been successfully tested with very encouraging results. In this paper we summarize the performance of the front-end electronics and present the response of the sensor to ionizing radiation