L. S. Tan

A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack

We report a novel surface passivation technology employing a silane-ammonia gas mixture to realize very high quality high-k gate dielectric on GaAs. This technology eliminates the poor quality native oxide while forming an ultrathin silicon oxynitride (SiOxNy) interfacial passivation layer between the high-k dielectric and the GaAs surface. Interface state density Dit of about 1 times 1011 eV-1 cm-2 was achieved, which is the lowest reported value for a high-k dielectric formed on GaAs by CVD, ALD, or PVD techniques. This enables the formation of high quality gate stack on GaAs for high performance CMOS applications. We also realized the smallest reported (160 nm gate length) inversion-type enhancement-mode surface channel GaAs MOSFET. The surface-channel GaAs MOSFETs in this work has demonstrated one of the highest peak electron mobility of ~2100 cm2/Vmiddots. The lowest reported subthreshold swing (~100 mV/decade) for surface-channel GaAs MOSFETs was also achieved for devices with longer gate length. Extensive bias-temperature instability (BTI) characterization was performed to evaluate the reliability of the gate stack.

Silane–Ammonia Surface Passivation for Gallium Arsenide Surface-Channel n-MOSFETs

A novel surface passivation technology employing silane (SiH4) and ammonia (NH3) was demonstrated to realize high-quality metal-gate/high-k dielectric stack on GaAs. In addition to ex situ cleaning/passivation and in situ vacuum anneal to remove the native oxide on GaAs, the key improvements reported in this letter include the introduction of NH3 in a SiH4 passivation to form a SiN passivation layer that protects the GaAs surface from exposure to the oxidizing ambient during high- k dielectric deposition. Negligible As-O and Ga-O bonds were found. This passivation technology was integrated in a metal-organic chemical-vapor deposition tool. Inversion-type GaAs n-MOSFETs were fabricated with the SiH4 and NH3 passivation technology, showing good electrical characteristics with a peak effective mobility of 1920 cm2/V middots, an I on/I off ratio of ~ 105, and a subthreshold swing of ~ 98 mV/dec, in surface-channel GaAs MOSFETs with a gate length of 2 mum.

In situ Surface Passivation of Gallium Nitride for Metal–Organic Chemical Vapor Deposition of High-Permittivity Gate Dielectric

We report the demonstration of novel techniques for surface passivation of gallium nitride (GaN), comprising the steps of in situ vacuum anneal (VA) and silane-ammonia (SiH₄ + NH₃) or silane (SiH₄) treatment for GaN, prior to the formation of high-permittivity gate dielectric in a multichamber metal-organic chemical vapor deposition tool. The effects of VA temperature and the SiH₄ + NH₃ or SiH₄ treatment temperature on interface quality was investigated. High-temperature capacitance-voltage characterization was also performed to probe the interface states near the midgap of GaN. Interface state density D_it as a function of energy was extracted. Without in situ passivation, a control TaN/HfAlO/GaN capacitor has a midgap D_it of ~2.0 × 10¹² cm^-2 · eV^-1. This is reduced to ~4.0 × 10¹¹ cm^-2 · eV^-1 and ~2.0 × 10¹⁰ cm^-2 · eV^-1 for samples that received the in situ SiH₄ + NH₃ treatment and in situ SiH₄ treatment, respectively.

Impact of In situ vacuum anneal and SiH4 treatment on electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors

The effect of in situ vacuum anneal (VA) and silane (SiH4) treatment on the electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors was investigated. Native Ga-O bonds on the AlGaN surface can be completely removed by this in situ passivation technique, which was confirmed by x-ray photoelectron spectroscopy. In situ VA and SiH4 passivation also reduced the device gate leakage current. This is attributed to the suppression of trap-assisted tunneling current through the HfAlO gate dielectric. Saturation drain current for devices with in situ VA and SiH4 passivation was also improved, which is due to increased two-dimensional electron gas density. In addition, devices with in situ VA and SiH4 passivation achieved an Ion/Ioff ratio of around 106 and a subthreshold swing of less than 100 mV/decade.

Local stress induced by diamond-like carbon liner in AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors and impact on electrical characteristics

The device physics of AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor (MOS-HEMT) with localized stress introduced by a diamond-like carbon (DLC) liner or encapsulation layer was investigated. DLC film with high intrinsic compressive stress (∼6 GPa) formed over AlGaN/GaN MOS-HEMTs contributed local compressive stress in the channel region. This was found to reduce the two-dimensional electron gas (2-DEG) density in the channel, leading to a positive threshold voltage shift. Transconductance and drain current at a given gate overdrive were also improved. On the other hand, the DLC introduced local tensile stress in the region between the gate and source/drain contacts, leading to a localized increase in 2-DEG density, giving reduced series resistance. The results of this work are expected to be useful for strain engineering of AlGaN/GaN MOS-HEMTs.

Study of electron traps in semi‐insulating gallium‐arsenide buffer layers for the suppression of backgating by the zero‐bias thermally stimulated current technique

Electron traps in undoped‐GaAs epitaxial layers grown at low temperatures (<300 °C) by molecular beam epitaxy were studied by the zero‐bias thermally stimulated current technique. Four traps T1‐4 were detected in as‐grown samples. It was also found that all the traps detected can be annealed out except the T1 trap. However, the buffer layer, with or without annealing, was found to be an effective remedy for backgating in high electron mobility transistors, indicating that the T1 trap may have a much more significant role than the three shallower traps in the suppression of backgating. The T1 trap is believed to be the EL3 electron trap which is related to oxygen contamination.

Trap signatures of As precipitates and As‐antisite‐related defects in GaAs epilayers grown by molecular beam epitaxy at low temperatures

Despite many separate studies of the two dominant defects, i.e., As precipitates and arsenic‐antisite (AsGa)‐related traps, in GaAs epilayers grown by molecular beam epitaxy at low temperatures, they are seldom examined simultaneously. In this letter, we report the detection of both defects in electron trap spectrum obtained by zero quiescent bias voltage transient current spectroscopy. The As precipitates appear as a broad continuum of states in the lower temperature region (<280 K) of the spectra whereas the AsGa‐related defect appears as a discrete peak at a higher temperature. The AsGa‐related trap has an activation energy of 0.65 eV and a capture cross section of 9.3×10−14 cm2. It is found that the trap characteristic of low temperature GaAs is strongly dependent on its growth temperature and the above mentioned defects may not dominate in some cases.

High oxygen and carbon contents in GaAs epilayers grown below a critical substrate temperature by molecular beam epitaxy

By quantitative secondary ion mass spectroscopy (SIMS) analyses, oxygen and carbon contents in GaAs epitaxial layers grown by molecular beam epitaxy (MBE) were found to increase significantly when the growth temperature was reduced below a critical value at about 450 °C. The concentrations of oxygen and carbon in GaAs epilayers grown below the critical temperature were about 4×1017 cm−3 and 3×1016 cm−3, respectively. Meanwhile, impurity accumulation during growth interruption became faster resulting in even higher interfacial impurity concentrations. Oxygen and carbon will affect the electrical properties of the GaAs epilayers, especially those grown between 350 °C and 450 °C where defects related to excess As may not be dominating.

AlGaN/GaN-on-Sapphire MOS-HEMTs with Breakdown Voltage of 1400 V and On-State Resistance of 22 mΩ.cm2 using a CMOS-Compatible Gold-Free Process

On-State Resistance of 22 mΩ.cm using a CMOS-Compatible Gold-Free Process Xinke Liu, Chunlei Zhan, Kwok Wai Chan, Wei Liu, Dong Zhi Chi, Leng Seow Tan, Kevin Jing Chen, and Yee-Chia Yeo. 1 Dept. of Electrical and Computer Engineering, National University of Singapore, 117576 Singapore. 2 Dept. of Electrical and Computer Engineering, Hong Kong University of Science and Technology, Kowloon, Hong Kong. 3 Luminous! Centre of Excellence for Semiconductor Lighting and Displays, Nanyang Technological University, 639785 Singapore. 4 Institute of Materials Research and Engineering, Agency for Science Technology and Research, 117602 Singapore.

Effects of in situ Surface Passivation of AlGaN/GaN MOS-HEMT: A Simulation Study

AlGaN/GaN heterostructure devices are very attractive for high power [1] and high frequency [2] applications. Advances in metal-oxide semiconductor high electron mobility transistor (MOSHEMT) technology have led to low gate leakage current [3]. However, it is believed that surface-related charge trapping at the insulator/AlGaN interface limits the performance of AlGaN/GaN MOS-HEMTs [4]. It was shown recently that in situ passivation of this interface during fabrication can enhance the performance of the AlGaN/GaN MOS-HEMT. [5].