Hock-Chun Chin

III–V Multiple-Gate Field-Effect Transistors With High-Mobility

We report an In_0.7Ga_0.3As n-channel multiple-gate field-effect transistor (MuGFET), featuring a lightly doped high-mobility channel with 70% indium and an epi-controlled retrograde-doped fin structure to suppress short-channel effects (SCEs). The retrograde well effectively reduces subsurface punch-through in the bulk MuGFET structure. The multiple-gate structure achieves good electrostatic control of the channel potential and SCEs in the In_0.7Ga_0.3As n-MuGFETs as compared with planar In_0.7Ga_0.3As MOSFETs. The In_0.7Ga_0.3As n-MuGFET with 130-nm channel length demonstrates a drain-induced barrier lowering of 135 mV/V and a drive current exceeding 840 μA/μm at V_DS = 1.5 V and V_GS - V_T = 3 V.

\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}

We report the first demonstration of a strained In_0.53 Ga_0.47As channel n-MOSFET featuring <i>in</i> <i>situ</i> doped In_0.4Ga_0.6As source/drain (S/D) regions. The <i>in</i> <i>situ</i> silicondoped In_0.4Ga_0.6As S/D was formed by a recess etch and a selective epitaxy of In_0.4Ga_0.6As in the S/D by metal-organic chemical vapor deposition. A lattice mismatch of ~ 0.9% between In_0.53Ga_0.47As and In_0.4 Ga_0.6As S/D gives rise to lateral tensile strain and vertical compressive strain in the In_0.53Ga_0.47As channel region. In addition, the <i>in</i> <i>situ</i> Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted In_0.53Ga_0.47As S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.

Channel and Epi-Controlled Retrograde-Doped Fin

In this letter, we report a novel n-channel GaAs MOSFET featuring TaN/HfAlO/GaAs gate stack with in situ surface passivation (vacuum anneal and silane treatment), alternative gold-free palladium-germanium (PdGe) source and drain (S/D) ohmic contacts, and silicon plus phosphorus coimplanted S/D regions. With the novel in situ surface passivation, excellent capacitance-voltage characteristics with low-frequency dispersion and small stretch-out can be achieved, indicating low interface state density. This surface-channel GaAs device exhibits excellent transistor output characteristics with a high drain current on/off ratio of 105 and a high peak electron mobility of 1230 cm2/V ldr s. In addition, gold contamination concerning CMOS technology can be alleviated with the successful integration of low-resistance PdGe ohmic contacts.

Lattice-Mismatched

We report a novel surface passivation technology employing a silane-ammonia gas mixture to realize very high quality high-k gate dielectric on GaAs. This technology eliminates the poor quality native oxide while forming an ultrathin silicon oxynitride (SiOxNy) interfacial passivation layer between the high-k dielectric and the GaAs surface. Interface state density Dit of about 1 times 1011 eV-1 cm-2 was achieved, which is the lowest reported value for a high-k dielectric formed on GaAs by CVD, ALD, or PVD techniques. This enables the formation of high quality gate stack on GaAs for high performance CMOS applications. We also realized the smallest reported (160 nm gate length) inversion-type enhancement-mode surface channel GaAs MOSFET. The surface-channel GaAs MOSFETs in this work has demonstrated one of the highest peak electron mobility of ~2100 cm2/Vmiddots. The lowest reported subthreshold swing (~100 mV/decade) for surface-channel GaAs MOSFETs was also achieved for devices with longer gate length. Extensive bias-temperature instability (BTI) characterization was performed to evaluate the reliability of the gate stack.

\hbox{In}_{0.4}\hbox{Ga}_{0.6} \hbox{As}

A surface passivation technique for GaAs that comprises in situ vacuum anneal and silane (SiH 4 ) treatment and that is compatible and can be easily integrated with a matured metallorganic chemical vapor deposition high-k gate dielectric process module is demonstrated. Extensive investigation of the dependence of electrical characteristics of TaN/HfA1O/GaAs gate stacks on process conditions, including in situ vacuum anneal and SiH 4 treatment temperatures, postgate-dielectric deposition anneal, and forming gas anneal conditions, is reported. It is shown that excellent capacitance-voltage characteristics with low-frequency dispersion, small hysteresis, and low midgap interface state density D it of 2.8-4.8 X 10 11 cm -2 eV -1 can be achieved with optimum processing conditions. The passivation technique reported here enables the fabrication of a self-aligned n-metal oxide semiconductor field-effect transistor, exhibiting good transfer characteristics with high peak carrier mobility of 1154 cm 2 /V s. The incorporation of Si + and P + coimplantation for achievement of high dopant activation in deep source and drain (S/D) regions and complementary metal oxide semiconductor compatible gold-free-based PdGe S/D ohmic contacts were also demonstrated.

Source/Drain Stressors With In Situ Doping for Strained

A novel surface passivation technology employing silane (SiH4) and ammonia (NH3) was demonstrated to realize high-quality metal-gate/high-k dielectric stack on GaAs. In addition to ex situ cleaning/passivation and in situ vacuum anneal to remove the native oxide on GaAs, the key improvements reported in this letter include the introduction of NH3 in a SiH4 passivation to form a SiN passivation layer that protects the GaAs surface from exposure to the oxidizing ambient during high- k dielectric deposition. Negligible As-O and Ga-O bonds were found. This passivation technology was integrated in a metal-organic chemical-vapor deposition tool. Inversion-type GaAs n-MOSFETs were fabricated with the SiH4 and NH3 passivation technology, showing good electrical characteristics with a peak effective mobility of 1920 cm2/V middots, an I on/I off ratio of ~ 105, and a subthreshold swing of ~ 98 mV/dec, in surface-channel GaAs MOSFETs with a gate length of 2 mum.

\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}

We report the first demonstration of an in situ surface-passivation technology for a GaN substrate using vacuum anneal (VA) and silane ( SiH4) treatment in a metal-organic chemical vapor deposition multichamber tool. Excellent electrical properties were obtained for TaN/HfAlO/GaN capacitors. Interface state density Dit was measured from midgap to near-conduction-band edge (EC) using the conductance method at high temperatures, and the lowest Dit of 1 × 1011 cm-2 · eV-1 at the midgap was achieved. Multiple frequency capacitance-voltage (C-V) measurement (10, 400, and 500 kHz) showed little frequency dispersion. Furthermore, the TaN/HfAlO/GaN stack was studied using high-resolution transmission electron microscopy, and the effectiveness of passivation using VA and SiH4 was evaluated using high-resolution X-ray photoelectron spectroscopy. The method reported here effectively removes the native oxide and passivates the GaN surface during the high-k dielectric-deposition process.

Channel n-MOSFETs

A novel n-channel strained SOI transistor featuring silicon-carbon (SiC) source/drain (S/D) regions and tensile stress silicon nitride (SiN) liner is demonstrated for the first time. Drive current IDsat enhancement contributed by the dual stressors is found to be additive and a significant increase in IDsat of 55% is observed at a gate length LG of 50 nm. In addition, we report the dependence of drive current on channel orientation, with highest I Dsat observed for strained n-MOSFETs with the |010| channel direction. A study of the carrier transport characteristics indicate reduced channel back-scattering and enhanced carrier injection velocity due to the strain effects

In Situ Surface Passivation and CMOS-Compatible Palladium–Germanium Contacts for Surface-Channel Gallium Arsenide MOSFETs

We report performance optimization techniques for FinFETs with Si _0.99C_0.01 source and drain (S/D) regions and sub-30 nm gate lengths. By scaling up the Si_0.99C_0.01 stressor thickness, a ~9% I_Dsat enhancement can be obtained. A further 16% I_Dsat enhancement can be achieved with the adoption of slim spacers. Carrier backscattering study was performed to clarify the carrier transport characteristics such as ballistic efficiency and carrier source injection, showing consistency with observed I_Dsat enhancement

A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack

A novel 80 nm gate length strained-Si n-channel transistor structure with lattice-mismatched source and drain (S/D) formed on thin-body silicon-on-insulator substrate is reported. The strained transistor features silicon-carbon (Si1-yCy) S/D regions, which are pseudomorphically grown by selective epitaxy. The incorporated carbon mole fraction y is 0.01. The lattice mismatch between Si0.99C0.01 and Si results in lateral tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The implementation of the Si0.99C0.01 stressors provides a substantial drive current IDsat enhancement of 11% over a control transistor at a gate length of 80 nm and a width of ~1.1 mum, while the enhancement for the linear drive current IDlin is approximately two times larger. Pulse measurements were also performed to correct for self-heating effects