Xinke Liu

Formation kinetics of fractal nanofiber networks in organogels

The fractal structure of nanofiber networks formed in organogels is identified, using an in situ rheological method, together with a coupled supercritical fluid CO2 extraction/scanning electron microscopy technique. The rheological method allows us to have in-line measurements of the fractal growth of the nanofiber networks. In comparison with conventional light scattering techniques, the results obtained from this technique show much less scatter in data. Unlike conventional fractal aggregates, the growth of this type of fractal pattern is governed by a noncrystallographic branching mechanism, which occurs via self-mismatch nucleation and growth.

Lattice-Mismatched

We report the first demonstration of a strained In_0.53 Ga_0.47As channel n-MOSFET featuring <i>in</i> <i>situ</i> doped In_0.4Ga_0.6As source/drain (S/D) regions. The <i>in</i> <i>situ</i> silicondoped In_0.4Ga_0.6As S/D was formed by a recess etch and a selective epitaxy of In_0.4Ga_0.6As in the S/D by metal-organic chemical vapor deposition. A lattice mismatch of ~ 0.9% between In_0.53Ga_0.47As and In_0.4 Ga_0.6As S/D gives rise to lateral tensile strain and vertical compressive strain in the In_0.53Ga_0.47As channel region. In addition, the <i>in</i> <i>situ</i> Si-doping process increases the carrier concentration in the S/D regions for series-resistance reduction. Significant drive-current improvement over the control n-MOSFET with Si-implanted In_0.53Ga_0.47As S/D regions was achieved. This is attributed to both the strain-induced band-structure modification in the channel that reduces the effective electron mass along the transport direction and the reduction in the S/D series resistance.

\hbox{In}_{0.4}\hbox{Ga}_{0.6} \hbox{As}

We report a novel surface passivation technology employing a silane-ammonia gas mixture to realize very high quality high-k gate dielectric on GaAs. This technology eliminates the poor quality native oxide while forming an ultrathin silicon oxynitride (SiOxNy) interfacial passivation layer between the high-k dielectric and the GaAs surface. Interface state density Dit of about 1 times 1011 eV-1 cm-2 was achieved, which is the lowest reported value for a high-k dielectric formed on GaAs by CVD, ALD, or PVD techniques. This enables the formation of high quality gate stack on GaAs for high performance CMOS applications. We also realized the smallest reported (160 nm gate length) inversion-type enhancement-mode surface channel GaAs MOSFET. The surface-channel GaAs MOSFETs in this work has demonstrated one of the highest peak electron mobility of ~2100 cm2/Vmiddots. The lowest reported subthreshold swing (~100 mV/decade) for surface-channel GaAs MOSFETs was also achieved for devices with longer gate length. Extensive bias-temperature instability (BTI) characterization was performed to evaluate the reliability of the gate stack.

Source/Drain Stressors With In Situ Doping for Strained

A novel surface passivation technology employing silane (SiH4) and ammonia (NH3) was demonstrated to realize high-quality metal-gate/high-k dielectric stack on GaAs. In addition to ex situ cleaning/passivation and in situ vacuum anneal to remove the native oxide on GaAs, the key improvements reported in this letter include the introduction of NH3 in a SiH4 passivation to form a SiN passivation layer that protects the GaAs surface from exposure to the oxidizing ambient during high- k dielectric deposition. Negligible As-O and Ga-O bonds were found. This passivation technology was integrated in a metal-organic chemical-vapor deposition tool. Inversion-type GaAs n-MOSFETs were fabricated with the SiH4 and NH3 passivation technology, showing good electrical characteristics with a peak effective mobility of 1920 cm2/V middots, an I on/I off ratio of ~ 105, and a subthreshold swing of ~ 98 mV/dec, in surface-channel GaAs MOSFETs with a gate length of 2 mum.

\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}

We report the first demonstration of an in situ surface-passivation technology for a GaN substrate using vacuum anneal (VA) and silane ( SiH4) treatment in a metal-organic chemical vapor deposition multichamber tool. Excellent electrical properties were obtained for TaN/HfAlO/GaN capacitors. Interface state density Dit was measured from midgap to near-conduction-band edge (EC) using the conductance method at high temperatures, and the lowest Dit of 1 × 1011 cm-2 · eV-1 at the midgap was achieved. Multiple frequency capacitance-voltage (C-V) measurement (10, 400, and 500 kHz) showed little frequency dispersion. Furthermore, the TaN/HfAlO/GaN stack was studied using high-resolution transmission electron microscopy, and the effectiveness of passivation using VA and SiH4 was evaluated using high-resolution X-ray photoelectron spectroscopy. The method reported here effectively removes the native oxide and passivates the GaN surface during the high-k dielectric-deposition process.

Channel n-MOSFETs

We report the demonstration of novel techniques for surface passivation of gallium nitride (GaN), comprising the steps of in situ vacuum anneal (VA) and silane-ammonia (SiH₄ + NH₃) or silane (SiH₄) treatment for GaN, prior to the formation of high-permittivity gate dielectric in a multichamber metal-organic chemical vapor deposition tool. The effects of VA temperature and the SiH₄ + NH₃ or SiH₄ treatment temperature on interface quality was investigated. High-temperature capacitance-voltage characterization was also performed to probe the interface states near the midgap of GaN. Interface state density D_it as a function of energy was extracted. Without in situ passivation, a control TaN/HfAlO/GaN capacitor has a midgap D_it of ~2.0 × 10¹² cm^-2 · eV^-1. This is reduced to ~4.0 × 10¹¹ cm^-2 · eV^-1 and ~2.0 × 10¹⁰ cm^-2 · eV^-1 for samples that received the in situ SiH₄ + NH₃ treatment and in situ SiH₄ treatment, respectively.

A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs N-MOSFET with 160 nm gate length and high-quality metal-gate/high-k dielectric stack

This paper reports the fabrication and characterization of AlGaN/GaN-on-sapphire metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) using a complementary metal–oxide–semiconductor (CMOS) compatible gold-free process. Devices with a gate-to-drain spacing LGD of 20 µm achieved an off-state breakdown voltage VBR of 1400 V and an on-state resistance Ron of 22 mΩcm2. This is the highest VBR achieved so far for gold-free AlGaN/GaN MOS-HEMTs. In addition, high on/off current ratio Ion/Ioff of ~109 and low gate leakage current IG of ~10-11 A/mm were also obtained.

Silane–Ammonia Surface Passivation for Gallium Arsenide Surface-Channel n-MOSFETs

This letter reports the fabrication and characterization of undoped AlGaN/GaN-on-silicon metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) using a complementary metal–oxide–semiconductor (CMOS) compatible gold-free process. Devices with a gate-to-drain LGD spacing of 5 µm achieved an off-state breakdown voltage VBR of 800 V and an on-state resistance Ron of 3 mΩcm2. In addition, subthreshold swing S of ~97 mV/decade and Ion/Ioff ratio of ~106 were obtained. Compared with those of gold-free GaN MOS-HEMTs having a gate-to-drain spacing LGD of less than 10 µm, the VBR achieved in this work is the highest.

High-Permittivity Dielectric Stack on Gallium Nitride Formed by Silane Surface Passivation and Metal–Organic Chemical Vapor Deposition

The device physics of AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor (MOS-HEMT) with localized stress introduced by a diamond-like carbon (DLC) liner or encapsulation layer was investigated. DLC film with high intrinsic compressive stress (∼6 GPa) formed over AlGaN/GaN MOS-HEMTs contributed local compressive stress in the channel region. This was found to reduce the two-dimensional electron gas (2-DEG) density in the channel, leading to a positive threshold voltage shift. Transconductance and drain current at a given gate overdrive were also improved. On the other hand, the DLC introduced local tensile stress in the region between the gate and source/drain contacts, leading to a localized increase in 2-DEG density, giving reduced series resistance. The results of this work are expected to be useful for strain engineering of AlGaN/GaN MOS-HEMTs.

In situ Surface Passivation of Gallium Nitride for Metal–Organic Chemical Vapor Deposition of High-Permittivity Gate Dielectric

For the first time, we reported AlGaN/GaN MOS-HEMTs enhanced by highly compressive DLC liner. ID,SAT enhancement of up to 30 % and peak transconductance increase of 22 % were obtained for DLC-strained devices with LG of less than 500 nm. Positive Vth shift of ∼1 V shows the potential of realizing enhancement mode AlGaN/GaN HEMTs with strain engineering. In situ silane technology was also integrated in the process flow in this work for drive current enhancement.