Lado Filipovic

Performance and stress analysis of metal oxide films for CMOS-integrated gas sensors.

The integration of gas sensor components into smart phones, tablets and wrist watches will revolutionize the environmental health and safety industry by providing individuals the ability to detect harmful chemicals and pollutants in the environment using always-on hand-held or wearable devices. Metal oxide gas sensors rely on changes in their electrical conductance due to the interaction of the oxide with a surrounding gas. These sensors have been extensively studied in the hopes that they will provide full gas sensing functionality with CMOS integrability. The performance of several metal oxide materials, such as tin oxide (SnO2), zinc oxide (ZnO), indium oxide (In2O3) and indium-tin-oxide (ITO), are studied for the detection of various harmful or toxic cases. Due to the need for these films to be heated to temperatures between 250 °C and 550 °C during operation in order to increase their sensing functionality, a considerable degradation of the film can result. The stress generation during thin film deposition and the thermo-mechanical stress that arises during post-deposition cooling is analyzed through simulations. A tin oxide thin film is deposited using the efficient and economical spray pyrolysis technique, which involves three steps: the atomization of the precursor solution, the transport of the aerosol droplets towards the wafer and the decomposition of the precursor at or near the substrate resulting in film growth. The details of this technique and a simulation methodology are presented. The dependence of the deposition technique on the sensor performance is also discussed.

The effects of etching and deposition on the performance and stress evolution of open through silicon vias

The effects of silicon etching using the Bosch process and LPCVD oxide deposition on the performance of open TSVs are analyzed through simulation. Using an in-house process simulator, a structure is generated which contains scalloped sidewalls as a result of the Bosch etch process. During the LPCVD deposition step, oxide is expected to be thinner at the trench bottom when compared to the top; however, additional localized thinning is observed around each scallop. The scalloped structure is compared to a structure where the etching step is not performed, but rather a flat trench profile is assumed. Both structures are imported into a finite element tool in order to analyze the effects of processing on device performance. The scalloped structure is shown to have an increased resistance and capacitance when compared to the flat TSV. Additionally, the scalloped TSV does not perform as well at high frequencies, where the signal loss is shown to increase. However, the scallops allow the TSV to respond better to an applied stress. This is due to the scallops’ enhanced range of motion and displacement, meaning they can compensate for the stress along the entire sidewall and not only on the TSV top, as in the flat structure. 2014 Elsevier Ltd. All rights reserved.

Modeling the Growth of Tin Dioxide Using Spray Pyrolysis Deposition for Gas Sensor Applications

In order for the gas sensor devices to enjoy the miniaturization trend that has consumed much of the electronic device industry, major research in the field is undertaken. The bulky sensor devices of previous generations can not easily be incorporated into a CMOS processing sequence, because of their bulky nature and potential higher cost of production. More recently, materials such as zinc oxide and tin dioxide have shown powerful gas sensing capabilities. Among many potential deposition methods, spray pyrolysis has become a popular approach because of its ease of use and cost effectiveness. A model for spray pyrolysis deposition is developed and implemented within the level set framework. The implementation allows for a smooth integration of multiple processing steps for the manufacture of smart gas sensor devices. From the observations, it was noted that spray pyrolysis deposition, when performed with a gas pressure nozzle, results in good step coverage, analogous to a CVD process. This is mainly due to the atomizing nozzle being placed at a reasonable distance away from the wafer surface and reducing the droplets volume and mass in order to ensure they fully evaporate prior to contact with the substrate surface. A topography simulator for this deposition methodology is presented.

Intrinsic stress analysis of tungsten-lined open TSVs

Abstract The effects of silicon etching and subsequent metallization during the fabrication of tungsten-lined open TSVs are examined using a combination of measurements and simulations. The total stress through a tungsten film deposited on a flat wafer is measured and finite element simulations are performed in order to identify the intrinsic and thermal stress components in the film. The data is then used to observe and model the stress through a TSV structure, which is etched using the DRIE process, resulting in scalloped inner sidewalls through the TSV opening. The scalloped structure is then compared to the ideal flat alternative with regard to the stress through the metal film and the TSVs electrical parameters, including resistance, capacitance, and inductance. It is found that the stress around the scallop varies significantly while the average stress through the tungsten in the flat TSV is only slightly higher than the stress observed through the scalloped structure. The resistance, capacitance, and inductance are all found to increase in the presence of scallops.

Effects of sidewall scallops on the performance and reliability of filled copper and open tungsten TSVs

The effects of the presence of scallops along the sidewalls of filled (copper) and open (tungsten) TSVs are studied. The Bosch process is used in order to generate highly vertical deep trenches; however, the process results in scallops along the etched sidewalls. A model for the Bosch process is implemented in an in-house level set simulator in order to generate various TSV structures with small and large sidewall scallops. The resulting geometries are imported into a finite element tool in order to analyze the performance and reliability of the devices. The electrical parameters of the TSVs are shown to vary when scallops are present for both types of TSVs. In addition, the maximum thermo-mechanical stress increases in the presence of scallops, while the average stress along the interfaces remains relatively unchanged. Electromigration analyses were also performed on the structures in order to determine stress development during the early stages of operation. It was found that the filled TSV with scalloped sidewalls experiences a higher current density and suffers from increased stress, while the sidewall scallops do not cause variation in the stress of open tungsten TSVs. The open tungsten TSVs experience most Electromigration-induced stress in the connecting metal layers and not along the sidewall.

A 10-bit low-power SAR ADC with a tunable series attenuation capacitor

A 10-bit successive approximation analog-to-digital converter (ADC), with offset correction circuitry and a tunable series attenuation capacitor is presented for implantable biosensor applications. The ADC is designed in a standard 0.13 ¿m CMOS process technology and can operate with supply voltages down to 0.6 V. The ADC uses MOSFETs that are designed to operate in the sub-threshold region of operation. The ADC achieved sample rates of up to 500 kS/s with all 1024 codes present and an INL and DNL of 0.1009LSB and 0.1429LSB respectively. A power dissipation of 20.9 pJ/cycle was measured, while operating at 100 kS/s, with a 0.6 V supply voltage and an INL and DNL of 0.2585LSB and 0.2862LSB respectively, with all codes present. With a 1.0 V VDD, a 320 kS/s signal achieved an INL and DNL of 0.1623LSB and 0.2858LSB, respectively, with all codes present. A series attenuation capacitor is used to reduce the size of the circuit. Since processing variations can change the value of this capacitor and degrade the ADC operation, it was designed to vary between 401.7 fF to 487.5 fF using five digital input bits. Without process variations, the optimal variable capacitor code was designed to be the middle code, ¿10000¿.

A monte carlo simulator for non-contact mode atomic force microscopy

Nanolithography using Non-Contact Mode Atomic Force Microscopy (NCM-AFM) is a promising method for the manufacture of nanometer sized devices. Compact models which suggest nanopatterned oxide dots with Gaussian or Lorentzian profiles are implemented in a Monte Carlo simulator in a level set environment. An alternative to compact models is explored with a physics based Monte Carlo model, where the AFM tip is treated as a point charge and the silicon wafer as an infinite conducting plane. The strength of the generated electric field creates oxyions which accelerate towards the silicon surface and cause oxide growth and surface deformations. A physics based model is presented, generating an oxide dot based on the induced surface charge density. Comparisons to empirical models suggest that a Lorentzian profile is better suited to describe surface deformations when compared to the Gaussian profile.

A simulator for local anodic oxidation of silicon surfaces

Models for the local anodic oxidation of silicon using scanning tunneling microscopy and non-contact atomic force microscopy are implemented in a generic process simulator, using the Level Set method. The advantage of the presented implementation is the ease with which further processing steps can be simulated in the same environment. An empirical model for the width of the oxide when using scanning tunneling microscopy is also presented and implemented with the simulator. An oxide dot is simulated for both processes, with a height of 1nm and widths of 5.6nm and 85nm, respectively. The simulator allows for a Gaussian or Lorentzian profile for the final surface deformation.

PARALLELIZATION STRATEGY FOR HIERARCHICAL RUN LENGTH ENCODED DATA STRUCTURES

An efficient parallelization strategy is presented for a Hierarchical Run Length Encoded (HRLE) data structure, implemented for the Sparse Field Level Set method. In order to achieve high parallel efficiency, computational work must be distributed evenly over all available CPU threads. Since the Level Set surface must be allowed to deform and evolve, thereby increasing the simulation area, there must exist a way to increase the surface domain while keeping an efficient parallelization strategy in place. This is achieved by processing the same number of calculations across each available CPU. The addition of data to HRLE data structures is only permitted in a sequential or lexicographical order, making parallelization more complex. The presented solution uses as many HRLE data structures as there are CPUs available. Approximately 90% of operations can be performed in parallel when using the presented strategy, leading to an efficiency of up to 96% or 78.5% when using two or sixteen CPU cores of an AMD Opteron 8435 processor, clocked at 2.6GHz, respectively. Topographies with one and two moving interfaces were simulated using multi-threading, showing the speedup and efficiency for the presented strategy.

Three-dimensional simulation of focused ion beam processing using the level set method

Three-dimensional simulations of focused ion beam milling, which use the level set method for surface evolution, are presented for the first time. This approach allows the inherent description of topological changes. The surface rates are calculated using Monte Carlo ray tracing in order to incorporate shadowing as well as redeposition. Parallelization is used to reduce the computation time.