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Dive into the research topics where Larry Wissel is active.

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Featured researches published by Larry Wissel.


Ibm Journal of Research and Development | 2008

Circuit design and modeling for soft errors

Aj Kleinosowski; Ethan H. Cannon; Phil Oldiges; Larry Wissel

As semiconductor devices decrease in size, soft errors are becoming a major issue that must be addressed at all stages of product definition. Even before prototype silicon chips are available for measuring, modeling must be able to predict soft-error rates with reasonable accuracy. As the technology matures, circuit test sites are produced and experimentally tested to determine representative fail rates of critical SRAM and flip-flop circuits. Circuit models are then fit to these experimental results and further test-site and product circuits are designed and modeled as needed.


IEEE Journal of Solid-state Circuits | 1992

Optimal usage of CMOS within a BiCMOS technology

Larry Wissel; Elliot L. Gould

The comparison of CMOS to BiCMOS often seen in the literature shows the delays of single-stage circuits driving a capacitive load, with the BiCMOS circuit exhibiting a bold advantage. This comparison is misleading, and it suggests that the highest possible performance chip design implemented in a BiCMOS technology, should use only BiCMOS circuits. When multistage circuits and chip wiring resistance are also considered, CMOS performance is found to be much closer to BiCMOS performance. CMOS circuits are shown to be preferred over BiCMOS circuits for a significant fraction of the chip nets. When nets that can afford a performance decrease are relaxed by using CMOS circuits instead of BiCMOS circuits, the CMOS fraction increases further. High usage of CMOS is desirable for area and yield considerations. Evaluations of the optimal CMOS role in future-generation BiCMOS technologies are expected to show an even larger role for CMOS. >


IEEE Transactions on Nuclear Science | 2009

Flip-Flop Upsets From Single-Event-Transients in 65 nm Clock Circuits

Larry Wissel; David F. Heidel; Michael S. Gordon; Kenneth P. Rodbell; Kevin Stawiasz; Ethan H. Cannon

This paper describes upsets of 65 nm flip-flops caused by Single-Event-Transients in clock-tree circuits. The upset rate is predicted through modeling, and compared to upset rates measured on a 65 nm test chip with 15 MeV carbon ions and 148 MeV protons.


custom integrated circuits conference | 2002

Managing soft errors in ASICs

Larry Wissel; Scott Pheasant; Rory Loughran; Chris LeBlanc; Bill Klaasen

Although the industry has long known about soft errors, customer awareness and concern about soft errors has recently increased. Advances in customer education, estimation techniques, and materials quality assist an ASIC designer in reducing soft-error system fails.


custom integrated circuits conference | 2003

Estimation of Iddq for early chip and technology design decisions

Terence B. Hook; Larry Wissel; David Mazgaj

Quiescent chip current (Iddq) has been known for many years, but its role has changed in just the past few years from a valuable means to screen for reliability to a demon threatening to derail the industrys phenomenal march of VLSI performance advances. Iddq originates with a phenomenon that is well-understood at the level of an individual transistor. However, at the chip level, both inter-chip and intra-chip process skew introduce wide and unexpected variation in Iddq. Despite these effects, meaningful predictions of Iddq can still be made at different points in the chip design cycle.


IEEE Transactions on Nuclear Science | 2008

Design Implications of Single Event Transients in a Commercial 45 nm SOI Device Technology

Aj Kleinosowski; Ethan H. Cannon; Jonathan A. Pellish; Phil Oldiges; Larry Wissel

This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets.


custom integrated circuits conference | 2007

A 550ps Access-Time Compilable SRAM in 65nm CMOS Technology

Larry Wissel; Harold Pilo; Chris LeBlanc; Xiaopeng Wang; Steve Lamphier; Michael T. Fragano

A fixed-configuration custom SRAM macro with a highly-scalable architecture was used as the basis for an ASIC SRAM compiler. The 256 Kb fixed-configuration uses dynamic circuitry (Pito et al., 2004) and other design techniques, and has been demonstrated in silicon to have an access time of 550 ps. The compilable SRAM extends the column mux options, and can be compiled from 2 Kb to 1.1 Mb. Novel circuitry is used for efficient redundancy implementation in both the row and column dimensions.


custom integrated circuits conference | 1991

Can CMOS resist the BiCMOS challenge

Larry Wissel; Elliot L. Gould

It is pointed out that the traditional CMOS-BiCMOS comparison of isolated circuits driving capacitive loads is not adequate. When multistage circuits and chip wiring resistance are also considered, CMOS is shown to be very competitive. In a high-performance BiCMOS logic chip design, 96% of the circuits can be converted to CMOS. For low-capacitance nets and nets with enough delay margin, CMOS is the clear preference due to its better density, circuit simplicity, lower sensitivity to wiring resistance, lower dl/dt and clear migration path to the next technology generation. CMOS is expected to remain the dominant circuit type for logic.<<ETX>>


custom integrated circuits conference | 2005

Modeling leakage in ASIC libraries

Susan K. Lichtensteiger; Larry Wissel; Jim Engel; Paul Sulva

Leakage is one of todays most important VLSI design issues, and ASIC design tools require accurate library leakage models. Leakage models have been traditionally derived from Spice simulation, but this approach is difficult and inflexible. Further, Spice simulation may not be possible for all IP in the library. We propose a new approach to modeling leakage of ASIC libraries. This approach is simple and flexible, and it is viable for all IP in the library. It requires no Spice simulation, yet its accuracy has been verified in silicon. It has been implemented for our 90nm ASICs


custom integrated circuits conference | 1996

Gate-array library design using local interconnect

Larry Wissel; Douglas W. Stout; Nathan C. Buck

An ASIC gate-array library has been created in 0.4 /spl mu/m CMOS technology using a local interconnect level. The gate-array cells in this library are denser than their counterparts in a library without local interconnect. The comparison of two benchmarks, including a 520K-gate ASIC routed with both libraries, further shows that the local interconnect allows higher density of ASIC designs due to more efficient use of the global inter-connect layers.

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