Phil Oldiges

FinFET design considerations based on 3-D simulation and analytical modeling

Design considerations of the FinFET have been investigated by three-dimensional (3-D) simulation and analytical modeling in this paper. Short-channel effects (SCE) of the FinFET can be reasonably controlled by reducing either silicon fin height or fin thickness. Analytical solution of 3-D Laplaces equation is employed to establish the design equations for the subthreshold behavior in the fully depleted silicon fins. Based on the 3-D analytical electrostatic potential in the subthreshold region, the threshold voltage (V/sub th/) roll-off and the subthreshold swing (S) are estimated by considering the source barrier changes in the most leaky channel path. V/sub th/ roll-off is an exponential function of the ratio of effective channel length to drain potential decay length, which can then be expressed as a function of the fin thickness, the fin height and the gate oxide thickness. The drain-potential decay lengths of single-gate fully depleted SOI MOSFET (FDFET), double-gate MOSFET (DGFET), rectangular surrounding-gate MOSFET (SGFET), and FinFET are compared. The drain potential scaling length and V/sub th/ roll-off can be included into a universal relation for convenient comparison.

2-D MOSFET modeling including surface effects and impact ionization by self-consistent solution of the Boltzmann, Poisson, and hole-continuity equations

We present a new two-dimensional (2-D) MOSFET simulation method achieved by directly solving the Boltzmann transport equation for electrons, the hole-current continuity equation, and the Poisson equation self-consistently. The spherical harmonic method is used for the solution of the Boltzmann equation. The solution directly gives the electron distribution function, electrostatic potential, and the hole concentration for the entire 2-D MOSFET. Average quantities such as electron concentration and electron temperature are obtained directly from the integration of the distribution function. The collision integral is formulated to arbitrarily high spherical harmonic order, and new collision terms are included that incorporate effects of surface scattering and electron-hole pair recombination/generation. I-V characteristics, which agree with experiment, are calculated directly from the distribution function for an LDD submicron MOSFET. Electron-hole pair generation due to impact ionization is also included by direct application of the collision integral. The calculations are efficient enough for day-to-day engineering design on workstation-type computers.

Alpha-particle-induced upsets in advanced CMOS circuits and technology

In this paper, we review the current status of single-event upsets caused by alpha-particles in IBM circuits and technology. While both alpha-particles and cosmic radiation can induce upsets, the alpha-particle-induced upset rate has become an increasingly important issue because alpha-particle-induced upsets are no longer limited to memory circuits. Latch circuits have become highly sensitive to alpha-particles. The alpha-particle-induced upset rate of latch circuits is one of the most critical issues for microprocessors requiring both high performance and high reliability.

Single-Event-Upset Critical Charge Measurements and Modeling of 65 nm Silicon-on-Insulator Latches and Memory Cells

Experimental and modeling results are presented on the critical charge required to upset exploratory 65 nm silicon-on-insulator (SOI) circuits. Using a mono-energetic, collimated, beam of particles the charge deposition was effectively modulated and modeled

Modeling Single-Event Upsets in 65-nm Silicon-on-Insulator Semiconductor Devices

This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the other connected between the body and source of the device. The physical representation of these two current sources is described in detail. Circuit modeling is verified against drift-diffusion field solver modeling and hardware experiments. The effects of manufacturing variation and operating condition variation on the qCrit of circuit storage elements are explored

Theoretical determination of the temporal and spatial structure of /spl alpha/-particle induced electron-hole pair generation in silicon

Physics-based modeling of the impact ionization process in silicon was performed to determine the time constants and radial distribution of electron-hole pairs after an /spl alpha/-particle strike. The radial distribution exhibited a Gaussian shape with a radius of approximately 50 nm. The impact ionization process took place over a period of less than approximately 500 fsec, implying time constants for use in semiconductor device simulations on the order of a few hundred fsec, a value much smaller than has been used in earlier device simulation work. Device simulations then show that the implication of using these shorter time constants is the creation of a higher concentration of electron-hole pairs at shorter times that cause stronger shunting effects for /spl alpha/-particle strikes between source and drain of MOS transistors.

Circuit design and modeling for soft errors

As semiconductor devices decrease in size, soft errors are becoming a major issue that must be addressed at all stages of product definition. Even before prototype silicon chips are available for measuring, modeling must be able to predict soft-error rates with reasonable accuracy. As the technology matures, circuit test sites are produced and experimentally tested to determine representative fail rates of critical SRAM and flip-flop circuits. Circuit models are then fit to these experimental results and further test-site and product circuits are designed and modeled as needed.

Electrostatic analysis of carbon nanotube arrays

In order to improve the performance of carbon nanotube field effect transistors (CNFETs), a nanotube array should be used. For a densely packed array of nanotubes, screening by nearby tubes affects the capacitance per tube. The gate-to-channel capacitance for a nanotube array of three different gate electrode configurations was examined in this study. Simulation results show that a wrap-around gate gives the largest gate-to-channel capacitance among the three gate configurations. A bottom gate structure, in which carbon nanotubes are unpassivated, presents a distinct electrostatic disadvantage of the weakest gate control. For a top gate structure, we found that an optimum design point exists for the pitch, which is defined as the distance between the centers of adjacent nanotubes, to get the largest gate capacitance per unit area.

Multi-bit upsets in 65nm SOI SRAMs

We study multi-bit upsets (MBU) in 65 nm SOI SRAMs. Proton beam and thorium foil experiments demonstrate that SOI SRAMs have lower soft error rate than bulk SRAMs. Monte Carlo SER simulations show that SOI SRAMs have a lower fraction of MBU than bulk SRAMs. The probability of MBU correlates with the spacing of sensitive devices in neighboring cells.

Ab initio Study of Metal Grain Orientation-Dependent Work Function and its Impact on FinFET Variability

A novel method to model the effect of local workfunction variation in high-k metal gate nanoscale transistors is proposed. Impact of variability in metal grain granularity on device performance is studied using ab initio density functional theory calculations and device simulations, which show that different metal grain orientations (GOs) can result in large (≥100 mV) variation in metal gate effective work function. Probabilities of occurrence of each GO and the grain size are used to estimate the work-function variations. Full 3-D device simulations are performed to study the effect of metal grain granularity on FinFET and planar MOSFET behavior. Simulated mismatch trends are shown to be in good agreement with the grain diameters and device geometries.