Lars Vestling

1 W/mm RF power density at 3.2 GHz for a dual-layer RESURF LDMOS transistor

In this letter, we present state-of-the-art performance, in terms of output power density, for an RF-power LDMOS transistor. The novel device structure has a dual-layer RESURF of the drift region, which allows for a sub-/spl mu/m channel length and a high breakdown voltage of 110 V. The output power density is more than 2 W/mm at 1 GHz and a V/sub DS/=70 V, with a stable gain of 23 dB at V/sub DS/=50 V. At 3.2 GHz the power density is over 1 W/mm at V/sub DS/=50 V and 0.6 W/mm at V/sub DS/=28 V. These results are to our knowledge the best ever for silicon power MOSFETs.

Drift region optimization of lateral RESURF devices

Abstract High-voltage lateral devices commonly uses the RESURF concept to achieve a high breakdown voltage. This however limits the conducting performance in the drift region due to the drift region charge that is determined by the RESURF criteria. This paper shows a method to overcome this limitation without effecting the breakdown voltage. The concept is to create a dual conducting device by introducing two extra layers in the drift region. Using the proposed method shows that the drift region resistance can be reduced with a factor 2 without significant reduction of the breakdown voltage. The substrate used is a CMOS substrate which makes it possible to use this concept in a conventional CMOS process.

A novel high-frequency high-voltage LDMOS transistor using an extended gate RESURF technology

A novel high-voltage DMOS transistor with a low doped extended gate is presented. The device withstands 240 V in the off-state and has a specific on-resistance of 24 m/spl Omega/cm/sup 2/. The transconductance is 60 mS/mm at 3 V gate voltage. The sub-micron channel length gives small-signal high-frequency performance as f/sub T/=2.8 GHz and f/sub max/=5.8 GHz and the unilateral power gain at 900 MHz is over 15 dB. The dependence of breakdown voltage and on-resistance on gate doping level and polysilicon gate length is investigated with device simulations. It is found that the breakdown voltage is highly dependent on the gate doping level.

Low resistivity SOI for substrate crosstalk reduction

Crosstalk in silicon-on-insulator (SOI)-substrates has been investigated using different equivalent circuit models and measurements on crosstalk test structures. The models reveal that a very low resistivity (LR) substrate (LR-SOI) can have significantly lower crosstalk, compared to both high resistivity and medium resistivity substrate. The low crosstalk for the LR-SOI is the result of effective shunting of the signal to ground through the low resistive substrate, which means that an effective substrate ground is crucial. Measurements on the crosstalk test structures also confirmed the results predicted by the models. The measurements show an improvement in the range of 20-40 dB for very low resistivity SOI substrates compared to high resistivity SOI substrates.

Analysis and design of a low-voltage high-frequency LDMOS transistor

For a low voltage lateral double-diffused MOS (LDMOS) transistor, the output performance has been improved in terms of f/sub MAX/. This is done by decreasing the output capacitance and thus decreasing the total output conductance. Extraction of the model parameters has been made and the most efficient parameter to improve was identified and linked to a specific part of the transistor structure. Layout changes in the n-well/p-base region were done as the result of the model analyses and finally, the modified devices were processed. Measurements on the improved devices showed results that closely, matched the expected, and f/sub MAX/ was increased with 30% and only a slight decrease in f/sub T/. Finally, the capacitance reduction in the n-well/p-base junction was measured by direct. measurements.

A capacitance-voltage measurement method for DMOS transistor channel length extraction

This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 /spl mu/m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.

Silicon-on-diamond MOS-transistors with thermally grown gate oxide

Summary form only given. Self-heating in Silicon-On-Insulator (SOI) devices has during the past years attracted lots of attention and is a problem that remains to be solved. It has, furthermore, been shown that in smart power devices, thick buried oxides of 3 /spl mu/m or more are desired to prevent the substrate potential to lower breakdown voltages. However, these thicker buried oxides will only aggravate the thermal limitations imposed by the buried oxide. Due to the outstanding thermal properties of diamond compared to silicon dioxide, it would consequently be advantageous if silicon dioxide could be replaced with diamond in future SOI materials. Even though it has been shown that diamond is compatible with conventional silicon processing, no MOS-transistors with thermally grown gate oxide has been manufactured up to date, due to the difficulty in protecting diamond during furnace oxidations. In this paper Silicon-On-Diamond (S-O-D) MOS-transistors with thermally grown gate oxide are presented for the first time.

Novel Silicon-on-SiC Substrate with Superior Thermal and RF Performance

A novel Si-on-SiC hybrid substrate is demonstrated using MOSFET devices. This is the first demonstration ever of this technology, to the best knowledge of the authors. The direct bonded substrate uses polysilicon as an intermediate layer, thereby eluding the thermally unfavourable SiO2. The MOSFET characteristics as well as the absence of self-heating effects are shown and are benchmarked against devices on commercially available epitaxial and SOI wafers, as well as Si-on-poly -SiC (SoPSiC, PicoGiga). Previous efforts to improve the thermal properties by replacing the SiO2 insulator have included diamond, AIN, and Al2O3.

Investigation of SOI-LDMOS for RF-Power Applications Using Computational Load Pull

Small-signal and computational load-pull simulations are used to investigate the effect of substrate resistivity on efficiency in high-power operation of high-frequency silicon-on-insulator-LDMOS transistors. Identical transistors are studied on substrates with different resistivities. Using computational load pull, their high-power performance is evaluated. The results are compared to previous investigations, relating the off-state output resistance to high-efficiency operation. From the large-signal simulation, an output circuit model based on a load-line match is extracted with parameters traceable from small-signal simulations. It is shown that, albeit high off-state output resistance is a good indication, it is not sufficient for high efficiency in a high-power operation. The bias and frequency dependence of the coupling through the substrate makes a more detailed on-state analysis necessary. It is shown that very low resistivity and high-resistivity SOI substrates both result in a high efficiency at the studied frequency and bias point. It is also shown that a normally doped medium-resistivity substrate results in a significantly lower efficiency.

A CMOS Compatible Power MOSFET for Low Voltage GHz Operation

This paper presents a high performance microwave lateral double-diffused MOS (LDMOS) transistor for low voltage applications. The device is manufactured in an ordinary CMOS process without any complex processing steps. The device has a current gain cut-off frequency, fT of 6.5 GHz and a power gain cut-off frequency, fMAX, of 14 GHz. The power-added efficiency is 45 % and the output power is 25 dBm for a device with 2 mm gate width at 1 GHz.