Klas-Håkan Eklund

1 W/mm RF power density at 3.2 GHz for a dual-layer RESURF LDMOS transistor

In this letter, we present state-of-the-art performance, in terms of output power density, for an RF-power LDMOS transistor. The novel device structure has a dual-layer RESURF of the drift region, which allows for a sub-/spl mu/m channel length and a high breakdown voltage of 110 V. The output power density is more than 2 W/mm at 1 GHz and a V/sub DS/=70 V, with a stable gain of 23 dB at V/sub DS/=50 V. At 3.2 GHz the power density is over 1 W/mm at V/sub DS/=50 V and 0.6 W/mm at V/sub DS/=28 V. These results are to our knowledge the best ever for silicon power MOSFETs.

Drift region optimization of lateral RESURF devices

Abstract High-voltage lateral devices commonly uses the RESURF concept to achieve a high breakdown voltage. This however limits the conducting performance in the drift region due to the drift region charge that is determined by the RESURF criteria. This paper shows a method to overcome this limitation without effecting the breakdown voltage. The concept is to create a dual conducting device by introducing two extra layers in the drift region. Using the proposed method shows that the drift region resistance can be reduced with a factor 2 without significant reduction of the breakdown voltage. The substrate used is a CMOS substrate which makes it possible to use this concept in a conventional CMOS process.

Low resistivity SOI for substrate crosstalk reduction

Crosstalk in silicon-on-insulator (SOI)-substrates has been investigated using different equivalent circuit models and measurements on crosstalk test structures. The models reveal that a very low resistivity (LR) substrate (LR-SOI) can have significantly lower crosstalk, compared to both high resistivity and medium resistivity substrate. The low crosstalk for the LR-SOI is the result of effective shunting of the signal to ground through the low resistive substrate, which means that an effective substrate ground is crucial. Measurements on the crosstalk test structures also confirmed the results predicted by the models. The measurements show an improvement in the range of 20-40 dB for very low resistivity SOI substrates compared to high resistivity SOI substrates.

Integration of a novel high-voltage Giga-Hertz DMOS transistor into a standard CMOS process

A new type of DMOS transistor aimed at high voltage power amplifications in the Giga-Hertz region is integrated into a standard CMOS process. By optimising the design for high voltage and high frequency, remarkable good electrical behaviour is obtained. The frequency performance was measured to f/sub T/=4.6 GHz and f/sub MAX/=10 GHz for a device with a channel length of 0.3 /spl mu/m and a breakdown voltage V/sub BR//spl ges/60 V. For a similar device fabricated on the same chip and using the same process flow, but designed to handle voltages above 300 V, f/sub T/=1.8 GHz and f/sub MAX/=3.2 GHz were measured.

Power Characteristics of High Voltage LDMOS Transistors

A lateral double diffused DMOS (LDMOS) transistor has been integrated into a CMOS process. An effective RESURF of the drain drift region enables a high breakdown voltage of about 90V and GHz operation. The measured output power density is 1.4W/mm at 1GHz for a supply voltage of 70V. A power added efficiency (PAE) of 51% and an output power density of 1.2W/mm was obtained at 50V.

Efficient crosstalk reduction using very low resistivity SOI substrate

Significant reduction of the crosstalk for SOI substrates has been obtained through the use of very low resistivity substrate. Based on modeling, the effect of substrate doping and the buried oxide capacitance on SOI substrate crosstalk was investigated. To verify the modeling results 3D simulation and finally manufacturing and measurement of crosstalk on the test structures were made. Measurements, 3D simulation and modeling corresponds well and shows an improvement in the range of 20-40 dB for very low resistivity SOI substrates compared to high resistivity SOI substrates.

Comparison between Si-LDMOS and GaN-based microwave power transistors

We present in this paper a performance comparison between Si-LDMOSTs with an optimized structure for high breakdown voltage, and AlGaN/GaN power HFETs, based on DC-I/V, small-signal and RF power measurement results.

A new latch-free LIGBT on SOI

A new latch-free LIGBT on SOI is presented. The new device combines advantages from both LDMOS as well as LIGBT technologies; high breakdown voltage, high drive current density, low control voltages, at the same time eliminating latch-up problems. Breakdown voltage of over 200 V, on-state current density over 3 A/mm and latch-free operation is demonstrated.

Analysis and improvements of high frequency substrate losses for RF MOSFETs

High frequency substrate losses for RF MOSFETs are analyzed using numerical device simulation. An equivalent circuit model is developed which accurately describes the off-state losses. Based on the model significant improvements in terms of output resistance are demonstrated, using an optimized device on high resistivity substrate.