Lauri Sumanen

A 2-GHz wide-band direct conversion receiver for WCDMA applications

A 2-GHz direct conversion receiver for third-generation mobile communications using wide-band code division multiple access achieves -114-dBm sensitivity for 128-kb/s data at 4.096-Mcps spreading rate. The receiver is distributed on four dies. The active RC channel selection filter can be programmed to three different bandwidths from 5 to 20-MHz radio-frequency (RF) spacing; and the gain control is merged with filtering. RF and baseband chips use a 25-GHz, 0.3-/spl mu/m BiCMOS technology while the two analog-to-digital converters are implemented with a 0.5-/spl mu/m CMOS. The double-sideband noise figure is 5.1 dB at the 94-dB maximum voltage gain, and the IIP3 and ITP2 are -9.5 and +38 dBm, respectively, The receiver draws 128 mA from a 2.7-V supply.

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

A 10-bit 200 MS/s parallel pipeline ADC is presented. It consists of a front-end sample-and-hold circuit and four parallel pipelined component ADCs followed by a digital offset compensation. By incorporating double sampling both in the S/H circuit and the component ADCs a power dissipation of only 280 mW from a 3.0 V supply is achieved. The circuit is implemented with a standard 0.5 µm CMOS process occupying 7.4 mm2. According to the measurements, a DNL and INL of 0.8 LSB and 0.9 LSB, respectively, is achieved while the peak SFDR is 56 dB with a 200 MS/s sample rate.

CMOS dynamic comparators for pipeline A/D converters

Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are fully differential, i.e. both sensing and reference voltage inputs are balanced, consist only of a single stage, and feature zero DC power dissipation with a built-in threshold adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS process, are measured to determine the offset properties of the compared topologies.

A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters

A new fully differential CMOS dynamic comparator topology suitable for pipeline A/D converters with a low stage resolution is proposed. A thorough analysis of its function and a comparison to a widely used dynamic comparator are given in this paper. The proposed topology, based on two cross coupled differential pairs and switchable current sources, has a small power and area dissipation and it is shown to be very robust against transistor mismatch.

A self-calibrated pipeline ADC with 200MHz IF-sampling frontend

A 13-bit, 50-MS/s pipeline ADC with IF-sampling capability is presented. A high sampling linearity is obtained through the use of bootstrapped switches. A digital self-calibration algorithm with modified capacitor measurement scheme is employed to improve the accuracy of the first two pipeline stages. The prototype, implemented with a 0.35-μm BiCMOS (SiGe) technology, shows a 76.5-dB SFDR at a 194.2-MHz signal frequency and dissipates 715 mW power from a 2.9-V supply.

A CMOS quadrature baseband frequency synthesizer/modulator

A quadrature baseband frequency synthesizer/modulator IC has been designed and fabricated in a 0.5 μm CMOS. This quadrature baseband frequency synthesizer/modulator is intended for use in a wide variety of indoor/outdoor portable wireless applications in the 2.4–2.4835 GHz ISM frequency band. This frequency synthesizer/modulator is a capable of frequency and phase modulation. The major components are: a quadrature direct digital synthesizer, digital-to-analog converters and lowpass filters. By programming the quadrature direct digital synthesizer, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. The quadrature baseband direct digital synthesizer produces an 80 MHz frequency band. The quadrature baseband spectrum could be upconverted with off-chip mixers into the 2.4 GHz ISM frequency band. The chip has a complexity of 17,803 transistors with a die area of 24 mm2 and a core area of 9 mm2. The power dissipation is 496 mW at 3.3 V.

A digital self-calibration method for pipeline A/D converters

An area and power efficient digital self-calibration method for pipeline A/D converters is presented. The method compensates for errors related to MDACs capacitor mismatch, reference voltage inaccuracy, amplifier finite DC gain, and charge injection of the sampling switches by measuring the errors attached to each capacitor of an MDAC (multiplying DAC). From the measurements, carried out by the back-end ADC, correction coefficients are calculated. Simulations show more than 1.5-bit improvement in effective number of bits at 14-bit level.

A single-amplifier 6-bit CMOS pipeline A/D converter for WCDMA receivers

An embedded single-amplifier 6-bit 15.36 MS/s CMOS pipeline A/D converter for WCDMA receivers is presented. By sharing an operational amplifier with two sequential stages and by using a mismatch insensitive dynamic comparator a total power dissipation of only 12 mW from 2.7 V supply is achieved. Special emphasis is put on the reduction of substrate noise coupling from the ADCs to the low noise amplifier and a very good isolation is achieved. The ADCs are implemented in a 0.35-/spl mu/m BiCMOS technology using only CMOS transistors and occupying 0.45 mm/sup 2/. According to the measurements, a DNL and INL of 0.27 LSB and 0.18 LSB are achieved while the SFDR and SNDR are 50 dB and 36 dB, respectively.

A 10-bit high-speed low-power CMOS D/A converter in 0.2 mm/sup 2/

This paper describes design and implementation of a 10-bit current steering CMOS D/A converter for a direct digital synthesizer. A very small circuit area is achieved by constructing the binary weighted currents using two sized unit current sources. This structure also leads to low power consumption since no decoding logic is needed. The glitch energy is reduced by using properly overlapped and amplitude limited steering signals for the differential current switches. The measured DNL is 0.43 LSB and INL 0.35 LSB. According to simulations the circuit achieves >60 dBc SFDR at 250 MS/s sampling rate with power dissipation of 17 mW@3.3 V. The circuit is implemented in 0.5 /spl mu/m CMOS technology.

A wide-band direct conversion receiver with on-chip A/D converters

In wireless communications, the receiver architectures, which have on-chip channel selection filters like direct conversion or low-IF, are preferred to increase the integration level. Combining digital signal processing on the same chip with analog circuits would be desirable in the miniaturization. Some recent papers present highly integrated tranceivers with mixed-mode or digital circuits on the same chip. However, only little discussion or experimental results have been given on the potential problems related to the system. This paper focuses on the design aspects of the single-chip direct conversion receivers, and gives experimental results of the BiCMOS prototype. The chip includes RF front-end, analog baseband signal processing and 6-bit A/D converters on the same die. It operates in the third generation wideband CDMA wireless system at 2 GHz.