Marko Kosunen

Implementation of Cyclostationary Feature Detector for Cognitive Radios

Spectrum sensing is needed in cognitive radios to provide information about the surrounding radio spectrum. This enables cognitive radio system to communicate among existing radio systems without interfering them. This paper describes an FPGA implementation of a cyclostationary feature detector, which has an improved detection performance achieved by decimation of the cyclic spectrum. Decimation also provides a simple way to control detection time and, thus, allows trading the detection time to better probability of detection and vice versa. Measured detection performance is presented and detection of a 802.11g WLAN signal from air is demonstrated.

A Micropower

In this paper, a micropower interface IC for a capacitive 3-axis micro-accelerometer is presented. The IC is implemented in a 0.25-mum CMOS process. The fully-integrated sensor interface is based on a DeltaSigma sensor front-end that operates mechanically in an open-loop configuration and converts the acceleration signals directly into the digital domain, thus avoiding the use of separate analog-to-digital converters. A detailed analysis with transfer functions is presented for the front-end circuit. Furthermore, the interface IC includes a decimator, a frequency reference, a clock generator for the front-end, a voltage and current reference, the required reference buffers, and low-dropout regulators (LDOs) needed for system-on-chip power management. The interface IC provides operating modes with 12-bit resolution for 1 and 25 Hz signal bandwidths. The former is optimized for very low power dissipation at the cost of reduced bandwidth, and is intended for example for activity monitoring in otherwise powered-off devices. The chip, with a 1.73 mm2 active area, draws typically 21.2 muA in the 1 Hz mode, and 97.6 muA in the 25 Hz mode, from a 1.2-2.75 V supply. In the 1 and 25 Hz modes with a plusmn 4-g capacitive 3-axis accelerometer, the measured noise floors in the x-, y-, and z-directions are 1080, 1100 and 930 mug/radic{Hz}, and 360, 320 and 275 mug/radic{Hz} , respectively. The implemented prototype achieves competitive figures of merit (FOMs) compared to the other published or commercially available, low-g, low-power accelerometers.

\Delta\Sigma

A global system for mobile communication (GSM)/enhanced data rates for GSM evolution (EDGE)/wideband code division multiple access (WCDMA) modulator with a 14-bit on-chip digital-to-analog (D/A) converter is presented. The modulator consists of several digital signal processing building blocks, including a programmable pulse shaping filter, interpolation filters, resampler, co-ordinate rotation digital computer (CORDIC) rotator, programmable output power level controller and ramping unit, and x/sinx filter. The precompensation filter, which compensates the sinc droop above the Nyquist frequency, makes it possible to use WCDMA signal images for up-conversion. The new programmable up/down unit allows power ramping on a time-slot basis as specified for GSM, EDGE and time division duplex (TDD)-WCDMA. The multistandard modulator meets the spectral, phase and error vector magnitude (EVM) specifications. The die area of the chip is 22.09 mm/sup 2/ in 0.35-/spl mu/m CMOS technology. Power consumption is 1.7 W at 3.3 V with 110 MHz.

-Based Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

A multicarrier quadrature amplitude modulation (QAM) modulator has been developed and implemented with programmable logic devices. The multicarrier QAM modulator contains four CORDIC-based QAM modulators. A conventional QAM modulator needs two multipliers, one adder, and sine/cosine ROMs. The designed CORDIC-based QAM modulator has about the same logic complexity as the two multipliers and the adder with the same word sizes. Each QAM modulator accepts 13-bit in-phase and quadrature data streams, interpolates them by 16, and upconverts the baseband signal to a selected center frequency. The frequencies of the four carriers can be independently adjusted. The proposed multicarrier QAM modulator does not use an analog I/Q modulator, and therefore, the difficulties of adjusting the dc offset, phasing, and the amplitude levels between the in-phase and quadrature-phase signal paths are avoided. The multicarrier QAM modulator is designed to fulfil the spectrum and error vector magnitude (EVM) specifications of the wideband code-division multiple-access (WCDMA) system. The simulated EVM is 1.06% root mean square (rms), well below the specified 12.5% rms for WCDMA. The measured ratio of the integrated first/second/third adjacent channel power (4.096-MHz bandwidth) to the integrated channel power (4.096-MHz bandwidth) is -68.16/-68.24/-66.17 dB versus the specified -45/-55/-55 dB.

A GSM/EDGE/WCDMA modulator with on-chip D/A converter for base stations

Spectrum sensing is an essential part of future cognitive radios, as the spectrum sensor provides information about the utilization of the surrounding radio spectrum. Several approaches to implementing spectrum sensing have been proposed in the literature, one of them being the class of feature detectors. Cyclostationary feature detectors are, in general, considered to be superior in performance but suffer from high implementation complexity. Therefore, most studies still utilize energy detectors, which may not reach the performance requirements set for practical implementations. This paper presents angular domain feature detection algorithms that are based on cyclostationary properties. Angular domain signal processing is shown to simplify the implementation considerably while preserving comparable performance. Moreover, a new detection algorithm that leads to multiplier-free implementation and reduces the memory requirements, compared with any previous approaches, is proposed.

A multicarrier QAM modulator

A multicarrier QAM modulator has been developed and simulated. The multicarrier QAM modulator contains four upconversion circuits. Each upconverting circuit accepts 12 b in-phase and quadrature data streams, interpolates those by 16 and upconverts the baseband signal to a selected center frequency. The outputs of these upconverting circuits are combined together in the digital domain. The multicarrier QAM modulator was designed to fulfil the spectrum and error vector magnitude (EVM) specification of the wideband code division multiple access (WCDMA) system.

Correlation-Based Detection of OFDM Signals in the Angular Domain

A Direct Digital Synthesizer (DDS) with an on-chip D/A-converter is designed and processed in 0.8 µm BiCMOS. The digital parts of the chip are implemented with CMOS design to reduce power consumption. The 10-bit D/A-converter is designed with BiCMOS technology in order to operate at a clock rate of 150 MHz. At the 150 MHz clock frequency, the Spurious Free Dynamic Range (SFDR) is 60 dBc at low synthesized frequencies, decreasing to 52 dBc at high synthesized frequencies in the output frequency band (0 to 60 MHz). The DDS covers the output frequency band in steps of 0.0349 Hz with the frequency switching speed of 140 ns. The chip has a complexity of 19,100 transistors with a die/core area of 12.2/3.9 mm2. The power dissipation is 0.6W at 150MHz @ 5V. The maximum operating clock frequency of the chip is 170 MHz.

Multicarrier QAM modulator

In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpolation chain for data streams and four digital frequency synthesizer/modulators, which are based on a coordinate rotation digital computer (CORDIC) vector rotation algorithm. The interpolation chain consists of a root-raised cosine pulse shaping filter and three half-band filters for image filtering. The modulated carriers are combined to form a multicarrier WCDMA signal. The SINC-attenuation effect of a digital/analog (D/A) converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter, which is integrated on the same silicon chip. The modulator is implemented with a 0.35-mum BiCMOS process with CMOS transistors only

A direct digital synthesizer with an on-chip D/A-converter

A quadrature baseband frequency synthesizer/modulator IC has been designed and fabricated in a 0.5 μm CMOS. This quadrature baseband frequency synthesizer/modulator is intended for use in a wide variety of indoor/outdoor portable wireless applications in the 2.4–2.4835 GHz ISM frequency band. This frequency synthesizer/modulator is a capable of frequency and phase modulation. The major components are: a quadrature direct digital synthesizer, digital-to-analog converters and lowpass filters. By programming the quadrature direct digital synthesizer, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. The quadrature baseband direct digital synthesizer produces an 80 MHz frequency band. The quadrature baseband spectrum could be upconverted with off-chip mixers into the 2.4 GHz ISM frequency band. The chip has a complexity of 17,803 transistors with a die area of 24 mm2 and a core area of 9 mm2. The power dissipation is 496 mW at 3.3 V.

A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter

Detecting the presence of primary users and ability to find white spaces in the spectrum are the key enablers of the opportunistic communication. This paper analyzes the trade-offs in cyclostationary-based spectrum sensing algorithm implementations in terms of performance, hardware complexity, and power consumption. The evaluation of the algorithm implementations is performed on field-programmable gate arrays. The analysis presented will provide the designer understanding of dependency between algorithm complexity and power consumption, which is inherently limiting factor of implementation feasibility for cognitive mobile devices.