Mikko Waltari

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

A 10-bit 200 MS/s parallel pipeline ADC is presented. It consists of a front-end sample-and-hold circuit and four parallel pipelined component ADCs followed by a digital offset compensation. By incorporating double sampling both in the S/H circuit and the component ADCs a power dissipation of only 280 mW from a 3.0 V supply is achieved. The circuit is implemented with a standard 0.5 µm CMOS process occupying 7.4 mm2. According to the measurements, a DNL and INL of 0.8 LSB and 0.9 LSB, respectively, is achieved while the peak SFDR is 56 dB with a 200 MS/s sample rate.

CMOS dynamic comparators for pipeline A/D converters

Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are fully differential, i.e. both sensing and reference voltage inputs are balanced, consist only of a single stage, and feature zero DC power dissipation with a built-in threshold adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS process, are measured to determine the offset properties of the compared topologies.

A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters

A new fully differential CMOS dynamic comparator topology suitable for pipeline A/D converters with a low stage resolution is proposed. A thorough analysis of its function and a comparison to a widely used dynamic comparator are given in this paper. The proposed topology, based on two cross coupled differential pairs and switchable current sources, has a small power and area dissipation and it is shown to be very robust against transistor mismatch.

Timing skew insensitive switching for double sampled circuits

A novel switching arrangement is proposed to avoid the timing skew problems in double-sampled circuits. The modification is applied in a high-speed double-sampled S/H-circuit. Comparisons to a circuit with conventional switching show no degradation in circuit performance due to the modification. The validity of theoretical results is verified via fabrication and measurements of a prototype chip.

A self-calibrated pipeline ADC with 200MHz IF-sampling frontend

A 13-bit, 50-MS/s pipeline ADC with IF-sampling capability is presented. A high sampling linearity is obtained through the use of bootstrapped switches. A digital self-calibration algorithm with modified capacitor measurement scheme is employed to improve the accuracy of the first two pipeline stages. The prototype, implemented with a 0.35-μm BiCMOS (SiGe) technology, shows a 76.5-dB SFDR at a 194.2-MHz signal frequency and dissipates 715 mW power from a 2.9-V supply.

Reference voltage driver for low-voltage CMOS A/D converters

A circuit for generating reference voltages for an A/D converter is presented. The circuit consisting of a bandgap reference and a driver circuit capable of operating on sub 1-volt supply voltages. The circuit is designed using a standard 0.5 /spl mu/m CMOS technology. Simulations show maximum 0.24% variation in the generated reference voltage over a temperature range from -20/spl deg/C to 100/spl deg/C and a supply voltage range from 0.95 V to 1.50 V. The circuit is capable of driving a 2 pF switched capacitor load at 5 MHz clock rate while consuming 450 /spl mu/W of power from a 1.0 V supply.

A direct digital synthesizer with an on-chip D/A-converter

A Direct Digital Synthesizer (DDS) with an on-chip D/A-converter is designed and processed in 0.8 µm BiCMOS. The digital parts of the chip are implemented with CMOS design to reduce power consumption. The 10-bit D/A-converter is designed with BiCMOS technology in order to operate at a clock rate of 150 MHz. At the 150 MHz clock frequency, the Spurious Free Dynamic Range (SFDR) is 60 dBc at low synthesized frequencies, decreasing to 52 dBc at high synthesized frequencies in the output frequency band (0 to 60 MHz). The DDS covers the output frequency band in steps of 0.0349 Hz with the frequency switching speed of 140 ns. The chip has a complexity of 19,100 transistors with a die/core area of 12.2/3.9 mm2. The power dissipation is 0.6W at 150MHz @ 5V. The maximum operating clock frequency of the chip is 170 MHz.

A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter

In this paper, design and implementation of a multicarrier quadrature amplitude modulation (QAM) modulator for a wideband code division multiple access (WCDMA) base-station with a 14-bit on-chip D/A converter is described. The modulator is capable of modulating four carriers with four independent in phase (I) and quadrature (Q) data streams. The proposed modulator structure consists of an interpolation chain for data streams and four digital frequency synthesizer/modulators, which are based on a coordinate rotation digital computer (CORDIC) vector rotation algorithm. The interpolation chain consists of a root-raised cosine pulse shaping filter and three half-band filters for image filtering. The modulated carriers are combined to form a multicarrier WCDMA signal. The SINC-attenuation effect of a digital/analog (D/A) converter is canceled by an inverse-SINC predistortion filter. The multicarrier signal is converted to the analog domain with a 14-bit current steering D/A converter, which is integrated on the same silicon chip. The modulator is implemented with a 0.35-mum BiCMOS process with CMOS transistors only

A 220-MSample/s CMOS Sample-and-Hold Circuit Using Double-Sampling

A fully differential sample-and-hold (S/H) circuit using double-sampling is presented. Compared to a conventional S/H configuration with a similar opamp the double-sampling gives a factor of two increase in the sampling rate while maintaining comparable power consumption. The circuit is designed in a 0.5 μm CMOS technology. The measurements show 10-bit operation up to the Nyquist frequency at the sampling rate of 220 MS/s with 25 mW @ 3 V power dissipation.

A switched-opamp with fast common mode feedback

In this paper a switched-opamp with a fast common mode feedback (CMFB) circuit is presented. The fully differential two stage amplifier needs CMFB only for the second stage, and thus a fast and simple passive CMFB-circuit may be used. The amplifier is capable of 1 volt operation and has no limitation on the maximum supply voltage.