Jarkko Jussila

A single-chip multimode receiver for GSM900, DCS1800, PCS1900, and WCDMA

A single-chip, multimode receiver for GSM900, DCS1800, PCS1900, and UTRA/FDD WCDMA is introduced in this paper. The receiver operates at four different radio frequencies with two different baseband bandwidths. The presented chip uses a direct-conversion architecture and consists of a low-noise amplifier (LNA), downconversion mixers with on-chip local-oscillator I/Q generation, channel selection filters, and programmable gain amplifiers. In spite of four receive bands, only four on-chip inductors are used in the single-ended LNA. The repeatable receiver second-order input intercept point (IIP2) of over +42 dBm is achieved with mixer linearization circuitry together with a baseband circuitry having approximately +100-dBV out-of-band IIP2. The noise figure of the SiGe BiCMOS receiver is less than 4.8 dB in all GSM modes, and 3.5 dB in WCDMA. The power consumption from a 2.7-V supply in all GSM modes and in WCDMA mode is 42 and 50 mW, respectively. The silicon area is 9.8 mm/sup 2/ including the bonding pads.

A 1.2-V Highly Linear Balanced Noise-Cancelling LNA in 0.13-

In this paper, a current-to-voltage combiner is proposed to realize a highly linear, balanced noise-cancelling low-noise amplifier (LNA) capable of low-voltage operation. The current-to-voltage combiner, implemented in the load of the amplifier, converts the output currents of the parallel common-gate (CG) and common-source (CS) stages of the LNA to voltages, equalizes the amplitudes of the voltages, and combines the voltages to a single output voltage. Since only a CS stage and passive components are employed to cancel the noise and distortion due to the CG input impedance matching circuit, high linearity is achieved in spite of the low supply voltage of 1.2 V. The LNA achieves a noise figure (NF) of 3.0 dB at 2.1 GHz with an input-referred third-order intercept point (IIP3) of +10.5 dBm while consuming 10.5 mA from a 1.2-V supply. The amplifier is fabricated in 0.13-mum CMOS process.

\mu{\hbox{m}}

Wireless Internet is currently available in extended narrowband cellular systems. However, the wider channel bandwidths in third-generation systems will further improve multimedia services and capacity. The direct conversion receiver is a distinct alternative for wide-band direct sequence CDMA systems in high-speed cellular communications. However, the wide bandwidth in the 3.84 MHz transmission leads easily to large power consumption in the receiver, particularly when trading off with the dynamic range limitations of the direct conversion architecture. This design achieves 3.7 dB NF and -16 dBm IIP3 with only 22 mA. The single-chip receiver includes a low-noise amplifier (LNA), downconversion mixers, analog channel selection filters, variable-gain amplifiers (VGA), and 6 b A/D converters (ADC).

CMOS

This paper describes a receiver designed to meet the stringent power consumption requirements for sensor radio, which operates at 2.4-GHz ISM band with Bluetooth. To enable the reusability of the Bluetooth system, only slight changes are made in the radio parameters. The symbol rate is decreased and the increased modulation index removes the energy maximum from the channel center, which enables a low-complexity direct-conversion receiver solution. To meet the speed and power requirements, this receiver is fabricated in a 0.13-/spl mu/m CMOS process. The 3.4-mW direct-conversion demonstrator receiver includes a low-noise amplifier, which is merged with quadrature mixers, local oscillator buffers, and one analog baseband channel with a 1-bit limiter for analog-to-digital conversion. The receiver consumes 2.75 mA from a 1.2-V supply. The receiver achieves 47-dB voltage gain, 28-dB NF, -21-dBm IIP3, and +18-dBm IIP2.

A 22-mA 3.0-dB NF direct conversion receiver for 3G WCDMA

An RF front-end for dual-band, dual-mode operation is presented in this paper. The front-end consumes 22.5 mW from a 1.8 V supply and is designed to be used in direct conversion WCDMA and GSM receivers. The measured noise figure, gain, and IIP3 are 2.3 dB, 39.5 dB, and -19 dBm for GSM and 4.3 dB, 33 dB, and -14.5 dBm for WCDMA, respectively. The front-end has 27 dB gain control range in both systems.

2.4-GHz receiver for sensor applications

This paper describes calibration techniques for downconversion mixers used in integrated direct-conversion receivers. A method of achieving a high even-order intermodulation rejection is presented. Using the method presented, the receiver second-order input intercept point (IIP2) can always be improved by more than 20 dB. The minimum achieved receiver IIP2 after calibration is +38 dBm. A technique to enhance the I/Q-amplitude balance between the quadrature channels is also introduced. A single-balanced adjustable mixer is implemented as a part of a prototype direct-conversion receiver. The receiver chip consists of a low-noise amplifier, mixers and calibration circuitry, a divide-by-two circuit, local oscillator (LO) buffers for LO generation, and active baseband filters. The chip is fabricated using a 0.35-/spl mu/m SiGe BiCMOS process and is characterized at 900 MHz.

A dual-band RF front-end for WCDMA and GSM applications

This paper describes a low-voltage channel selection analog front end with continuous-time low-pass filters and on-chip tuning for a receiver in an IS-95 cellular phone. The filters were realized as balanced seventh-order elliptical g/sub m/C filters to achieve low current consumption. The transconductors were realized by using second-generation current conveyors (CCII) and resistors to achieve good intermodulation distortion performance. A novel CCII circuit topology was developed to fulfil the low supply-voltage requirement. The cutoff frequency tuning was implemented with capacitance matrices and a time-domain master-slave tuning circuit.

Calibration techniques of active BiCMOS mixers

A direct conversion RF front-end for 2.0 GHz WCDMA and 5.8 GHz WLAN applications is described. The measured double-sideband NF, IIP3 and voltage gain are 3.6 dB, -15.1 dBm and 29.5 dB for WCDMA, and 5.2 dB, -17.4 dBm and 26.5 dB for WLAN, respectively. The RF front-end consumes 22.3 mA in WCDMA mode and 23.1 mA in WLAN mode from a 2.7 V supply. The chip is fabricated using a 0.35 /spl mu/m 45 GHz SiGe BiCMOS process.

A 3-V continuous-time filter with on-chip tuning for IS-95

Evolution and design trade-offs of a high performance, low-voltage downconversion mixer for wireless direct conversion receivers (DCR) are studied in this paper. As a first step, a mixer with active loads and adjustable conversion gain is presented. Then a different mixer topology that provides high conversion gain without deteriorating the linearity and noise performance is discussed. Finally, this topology is found to be well suitable for very low-voltage applications and thus its design and voltage scalability is depicted. The presented mixers are designed using a 0.35-/spl mu/m BiCMOS process and characterized at 2 GHz frequency.

A direct conversion RF front-end for 2-GHz WCDMA and 5.8-GHz WLAN applications

A single-chip dual-mode direct-conversion RF receiver with an improved method for increasing the IIP2 of the downconversion mixer is described. An improved IIP2 over the 2-MHz baseband channel is achieved. The 0.35-/spl mu/m SiGe BiCMOS RF receiver achieves 3.2-dB NF and -13-dBm IIP3 in 2-GHz mode, and 7.4-dB NF and -17-dBm IIP3 in 5-GHz mode. The current consumption in 2-GHz mode is 29.6 mA and in 5-GHz mode 28.4 mA. The chip area is 5.1 mm/sup 2/.