Leena Paivikki Buchwalter

A CMOS-compatible process for fabricating electrical through-vias in silicon

In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming increasingly difficult and less effective, and a range of new two- and three-dimensional silicon integration technologies are needed to support next-generation systems. A silicon-carrier system-on-package (SOP) is an advanced packaging solution, enabling interconnection between ICs and other devices at densities far beyond those of current first-level packaging. Silicon-carrier employs fine pitch Cu damascene wiring, high-density solder pads/joins and high-yielding electrical through-vias. A novel approach to fabricating robust though-vias in silicon is described. The key design feature enabling large-area, uniform arrays to be produced with high yield is the annular via shape. As compared to a standard cylindrical via shape, the annular via is easier to integrate into a standard CMOS copper back-end-of-the-line (BEOL) process flow. Two process flows are compared: the first having the conductor metal within the gap of the insulated annulus itself, the second having a conducting metal core enclosed within the inner wall of the annulus. For the first process flow, two annular conductors, plated copper and CVD tungsten, are compared in terms of ease of integration, yield and susceptibility to failure during thermal stressing. Large area (45 times 48 mm) silicon carrier modules containing more than 51,000 electrically measurable through-vias are used to compare overall yield and robustness of each process. Results on deep thermal cycling, current carrying capacity and thermomechanical modeling are discussed. Wafer-level via testing is used to statistically distinguish between via chain opens caused by bond and assembly issues versus failures in the vias or integrated wiring structures. Through-via resistances on the order of ~10 mOmega are typical, and through-via yields of 99.98% at module level have been demonstrated

Characterization of micro-bump C4 interconnects for Si-carrier SOP applications

This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, high-current, high-density bump interconnections can be achieved for Si-carrier technology

Pb-free microjoints (50 /spl mu/m pitch) for the next generation microsystems: the fabrication, assembly and characterization

To support the next generation highly integrated microsystem with 3D silicon integration using fine pitch interconnection and Si carrier, we develop a fabrication and assembly process at IBM Research to produce solder micro-joints (fine pitch flip-chip interconnections) for our system-on-package (SOP) technology. We fabricate solder bumps with 25 mum (or less) in diameter on 50 mum pitch size, as well as 50 mum in diameter on 100 mum pitch size, at wafer level (200mm) by electroplating method. There are up to 10208 micro-bumps (25 mum) built on a chip surface less than 0.4 cm2. The process can be applied to various solder compositions, including eutectic SnPb, Pb-free (CuSn), AuSn and high Pb (3Sn97Pb) solders. The test matrix includes different solder/UBM (under bump metallization) combination. In this paper, the discussion focuses on the fabrication, assembly and characterization of the micro-joints made with of Pb-free (CuSn) and eutectic SnPb solders with Ni and/or Cu stack plating. The preliminary electrical and mechanical test results indicated that reliable and high yield micro-bumps can be successfully made with this fabrication and assembly process

Silicon Carrier with Deep Through-Vias, Fine Pitch Wiring and Through Cavity for Parallel Optical Transceiver

The design, fabrication, assembly and characterization of a novel silicon carrier package used for enabling a Tb/s parallel optical transceiver is reported. Electrical through-vias, high speed wiring and a through cavity for housing optoelectronic (OE) devices are critical features of the silicon carrier that allow high density integration of optical and electrical components on a single substrate, resulting in a small form factor system that is capable of meeting high bandwidth requirements of large computing systems. A novel hierarchical approach involving eutectic AuSn and SnPb solder systems and flip chip bonding technology is used to assemble the transceiver module. The optical system used for coupling light from the OE devices to waveguides is based on a relay lens that is integrated into the OE array. The measurement and model for alignment tolerance analysis showed constant coupling efficiency from the OE to waveguide over a range of plusmn 10 mum, giving an excellent margin for alignment. Electrical simulations and measurement of silicon carrier through-vias showed an insertion loss of better than 1 dB at 20 GHz. Simulations and measurements also exhibited an attenuation of 4.3 dB/cm at 20 GHz for high speed wiring on the silicon carrier, which was adequate for 20 Gbps data transmission over a channel length of 7 mm

System-on-package (SOP) technology, characterization and applications

A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may range from miniaturized consumer products such as integrated function cell phones to high performance computers. SOP technology and related chip stacking challenges have been investigated and robust technology options are reported. Silicon through-vias can be fabricated using copper, tungsten, composite or alternate conductors. Via design and structure are discussed for vias in thin silicon packages mounted on a supporting substrate as well as thick silicon package that can be handled without a supporting substrate. Fine-pitch, high bandwidth wiring has been fabricated, characterized and shows greatest bandwidth for shorter interconnection distances. Fine pitch area array solder interconnections have been fabricated and characterized electrically, mechanically and with accelerated reliability testing. These fine pitch interconnections can enable the high bandwidth wiring for chip-to-chip interconnection. Integrated decoupling capacitors have been fabricated using parallel plate and trench technology. The integrated decoupling capacitors can provide under-chip, low inductance bypassing to minimize noise from simultaneous switching noise. New fine pitch, area array test technology provides a path to wafer level test for known-good-die, functional test, and burn-in for the fine pitch chip I/O. Advanced microchannel cooling can be leveraged to support high power, close proximity chips and chip stacks for cooling > 300 W/cm2. This IBM research paper describes the design, technical challenges and progress for next generation SOP technology, chip stacking, characterization, and potential new applications

Reaction of polyaniline with NMP at elevated temperatures

Heating a dilute solution of polyaniline emeraldine base in 1-methyl-2 pyrrolidinone under nitrogen at elevated temperatures resulted in the reduction of PANI to its leucoemeraldine state. The product was identified by infra-red, ultraviolet-visible, and X-ray photoelectron spectroscopy, and characterized by cyclic voltammetry and gel permeation chromatography.