Chirag S. Patel

Channel Estimation for Amplify and Forward Relay Based Cooperation Diversity Systems

Cooperation diversity schemes have been proposed for cellular networks that permit a base station (or a mobile station) to relay signals to a destination receiver, thereby increasing the network coverage and reliability. The mobile relays either decode and forward (DF) or amplify and forward (AF) the received signal. Most existing analyses of cooperation diversity assumes perfect channel information at the receiver. A realistic assessment should consider the effects of practical channel estimation schemes. This paper considers pilot symbol aided channel estimation for cooperation diversity systems. Since the overall channel in AF systems is different from conventional cellular channels, the channel estimation problem is interesting and challenging and therefore our focus is on AF systems. The paper addresses issues such as the estimator design, pilot symbol spacing based upon realistic channel models, and an approximate bit error rate (BER) analysis that accounts for imperfect channel estimation.

Statistical properties of amplify and forward relay fading channels

Cooperation diversity schemes have been proposed for cellular networks that permit mobile stations to relay signals to a final destination, thereby increasing the network capacity and coverage. The mobile relays either decode and retransmit the received signal or simply amplify and forward (A & F) the signal. The overall channel from the source to the destination via the relay in A & F systems is double Gaussian with properties quite different from a typical cellular channel. Since very little is known about A & F relay fading channels, this paper considers their statistical properties such as the envelope probability density function, autocorrelation, level crossing rate, and system performance characteristics like frequency of outages and average outage durations. We briefly discuss the simulation of these channels and verify our analysis by simulations.

Simulation of Rayleigh-faded mobile-to-mobile communication channels

Mobile-to-mobile channels find increasing applications in futuristic intelligent transport systems, ad hoc mobile wireless networks, and relay-based cellular networks. Their statistical properties are quite different from typical cellular radio channels, thereby requiring new methods for their simulation. This paper proposes a double-ring model to simulate the mobile-to-mobile local scattering environment, and develops sum-of-sinusoids (SoS)-based models for simulating such channels. The proposed models produce waveforms having desired statistical properties with good accuracy, and also remove some drawbacks of an existing model derived by using the discrete line spectrum simulation method.

Power constrained design of multiprocessor interconnection networks

The paper considers the power constrained design of orthogonal multiprocessor interconnection networks. The authors present a detailed model of message latency as a function of topology, technology architecture, and power. This model is then used to analyze a number of interesting scenarios, providing a sound engineering basis for interconnection network design in these cases. For example, they have observed that under a fixed power constraint, the network dimension which achieves minimal latency is a slowly growing function of system size. In addition, as they increase the available power per node for a fixed system size, the dimension at which message latency is minimized shifts towards higher dimensional networks.

Comparative analysis of statistical models for the simulation of Rayleigh faded cellular channels

Several new sum-of-sinusoids models have recently been introduced for the simulation of Rayleigh fading channels. These models are statistical in nature implying that their simulation parameters such as the Doppler frequencies are random. They have been shown to accurately reproduce some of the desired statistical properties of the faded envelope such as the time autocorrelation and the level crossing rate. However, a comparative analysis of these models, hitherto scattered throughout the literature, is not available. This paper compares these models in terms of their complexity and performance. The performance assessment is based upon the variance of the time average statistical properties from their ideal ensemble averages.

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

Sea of Leads (SoL) is an ultrahigh density (>10/sup 4//cm/sup 2/) compliant chip input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of SoL. SoL can lead to enhancements in reliability, electrical performance, manufacturing throughput, and cost. A chip with 12 /spl times/ 10/sup 3//cm/sup 2/ compliant I/O leads is demonstrated. The mechanically compliant I/O leads are designed to enable wafer-level testing and eliminate the need for underfill between chips and printed wiring boards by mitigating thermo-mechanical expansion mismatches between the two. The fabrication of partially nonadherent, or slippery, leads is desirable as it allows the leads to freely undergo strain during thermal cycling. Compared to adherent metal leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Microindentation experiments show that a polymer film with embedded air gaps provides substantially higher compliance than a polymer film without embedded air gaps.

Sea-of-leads MEMS I/O interconnects for low-k IC packaging

Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.

Analysis of OFDM/MC-CDMA under channel estimation and jamming

The BER degradation caused by imperfect channel estimation as well as the adverse effect of jamming on pilot symbols, which are used for the channel estimation (CE), is often neglected while analyzing OFDM und MC-CDMA systems leading to over-optimistic results. Therefore, to provide a more realistic analysis, we analyze the vulnerability of pilot symbol aided CE schemes for OFDM/MC-CDMA systems to narrowband and partial band jamming. We derive closed form BER expressions for studying the effect of imperfect CE for OFDMA/MC-CDMA in the absence of jamming in a frequency selective Rayleigh fading environment. We extend these results via simulations and theory (wherever permitted by mathematical tractability) to account for jamming. Some possible solutions such as the use of boosted pilots and the use of jamming side information, whenever available, to excise the jammed pilots or provide MMSE equalization are proposed to reduce the impact of jamming on the CE.

Compliant wafer level package (CWLP) with embedded air-gaps for sea of leads (SoL) interconnections

Sea of Leads (SoL) is an ultrahigh I/O density (>10/sup 4/ leads per cm/sup 2/) compliant wafer level package (CWLP) that potentially enables terabit on/off chip electrical bandwidth as well as enhances on-chip high current (e.g. >290 A) distribution of a mixed-signal system-on-a-chip (SoC). The addition of embedded air-gaps may mitigate problems with thermal expansion between the chip and printed wiring board, increase effective compliance of the package for wafer level testing applications, and reduce the dielectric constant of the interconnect dielectric material. An SoL package with 12000/cm/sup 2/ leads has been designed and fabricated, along with a prototype SoL package with 1000/cm/sup 2/ leads on top of a dielectric layer containing embedded air-gaps.

Cost analysis of compliant wafer level package

Low cost package solutions are required by the semiconductor industry to meet the growing demand of high performance and high functionality in electronic products. In particular, the International Technology Roadmap for Semiconductors (ITRS) projects the package cost per pin to be as low as (0.30-1.26 cents) in 1999 to (0.27-0.93 cents) in 2005 to (0.24-0.68 cents) in 2011. To satisfy this need, a Compliant Wafer Level Package (CWLP) technology has been developed that: (a) packages all of the ICs intact on the wafer at once, and (b) fabricates all of the compliant Input/Output (I/O) connections monolithically in one step. Using discrete event simulations, a detailed manufacturing cost model for the CWLP is described. In contrast to the conventional packages where the cost of the package increases with the I/O count, the CWLP cost is independent of the I/O count because all of the I/Os are monolithically fabricated in one step. For 6-inch wafers and throughput greater than 50,000 wafers per year, the manufacturing cost of the CWLP is computed to be