Cornelia K. Tsang

Three-dimensional silicon integration

Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to-silicon fine-pitch interconnections offers many product benefits. Advantages of these emerging 3D silicon integration technologies can include the following: power efficiency, performance enhancements, significant product miniaturization, cost reduction, and modular design for improved time to market. IBM research activities are aimed at providing design rules, structures, and processes that make 3D technology manufacturable for chips used in actual products on the basis of data from test-vehicle (i.e., prototype) design, fabrication, and characterization demonstrations. Three-dimensional integration can be applied to a wide range of interconnection densities (<10/cm2 to 108/cm2), requiring new architectures for product optimization and multiple options for fabrication. Demonstration test structures, which are designed, fabricated, and characterized, are used to generate experimental data, establish models and design guidelines, and help define processes for future product consideration. This paper 1) reviews technology integration from a historical perspective, 2) describes industry-wide progress in 3D technology with examples of TSV and silicon-silicon interconnection advancement over the last 10 years, 3) highlights 3D technology from IBM, including demonstration test vehicles used to develop ground rules, collect data, and evaluate reliability, and 4) provides examples of 3D emerging industry product applications that could create marketable systems.

3D silicon integration

Three-dimensional (3D) chip integration may provide a path to miniaturization, high bandwidth, low power, high performance and system scaling. Integration options can leverage stacked die and/or silicon packages depending on applications. The enabling technology elements include: (i) through-silicon-vias (TSV) with thinned silicon wafers, (ii) fine pitch wiring, (iii) fine pitch interconnection between stacked die, (iv) fine pitch test for known-good die, and (v) power delivery, distribution and thermal cooling technology. Applications may range from miniaturization of portable electronics like image sensors and cell phones to power efficient, high performance computing solutions such as servers and super computers. Silicon based packaging and 3D stacked die technologies have been in research studies for more than a decade at IBM and in industry, universities & consortia. IBM research experiments have included test vehicle design, build, characterization and modeling. Robust structures and processes have been developed based on (i) process learning for silicon based structures, (ii) assembly process comparisons for fine pitch chip interconnection, (iii) electrical, mechanical and thermal characterization and (iv) reliability & accelerated stress characterization. TSV technology investigations have included composite, copper and tungsten metallurgies. Wiring demonstrations ranged from sub-micron fine pitch wiring line widths & spaces to larger dimensions. I/O interconnections investigated feature sizes such as 100 I/O / mm2, 400 I/O/mm2, and interconnection features sizes which support 2500 I/O / mm2. In addition, integrated decoupling capacitors of one hundred ten nano-farads per mm2 per layer and assembly of module structures on silicon packages with ceramic or organic base packages were demonstrated. Examples of robust TSV structures and characterization, single die with silicon interposers, multiple die on a silicon package and stacked die assemblies are given along with highlights of characterization including aspects of electrical, mechanical and reliability results. This research paper describes recent advances in industry and reports advancements from IBM in the design, technical challenges and progress toward 3D chip integration structures. In addition, examples of potential applications that may take advantage of 3D integration are discussed.

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections

Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.

A CMOS-compatible process for fabricating electrical through-vias in silicon

In the past, traditional CMOS scaling has been one of the principal levers to achieve increased system-level performance. Today, scaling is becoming increasingly difficult and less effective, and a range of new two- and three-dimensional silicon integration technologies are needed to support next-generation systems. A silicon-carrier system-on-package (SOP) is an advanced packaging solution, enabling interconnection between ICs and other devices at densities far beyond those of current first-level packaging. Silicon-carrier employs fine pitch Cu damascene wiring, high-density solder pads/joins and high-yielding electrical through-vias. A novel approach to fabricating robust though-vias in silicon is described. The key design feature enabling large-area, uniform arrays to be produced with high yield is the annular via shape. As compared to a standard cylindrical via shape, the annular via is easier to integrate into a standard CMOS copper back-end-of-the-line (BEOL) process flow. Two process flows are compared: the first having the conductor metal within the gap of the insulated annulus itself, the second having a conducting metal core enclosed within the inner wall of the annulus. For the first process flow, two annular conductors, plated copper and CVD tungsten, are compared in terms of ease of integration, yield and susceptibility to failure during thermal stressing. Large area (45 times 48 mm) silicon carrier modules containing more than 51,000 electrically measurable through-vias are used to compare overall yield and robustness of each process. Results on deep thermal cycling, current carrying capacity and thermomechanical modeling are discussed. Wafer-level via testing is used to statistically distinguish between via chain opens caused by bond and assembly issues versus failures in the vias or integrated wiring structures. Through-via resistances on the order of ~10 mOmega are typical, and through-via yields of 99.98% at module level have been demonstrated

Chip-to-chip optical interconnects

Terabus is based on a silicon-carrier interposer on an organic card containing 48 polymer waveguides. We have demonstrated 4times12 arrays of low power optical transmitters and receivers, operating up to 20 Gb/s and 14 Gb/s per channel respectively

3D copper TSV integration, testing and reliability

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

Terabit/s-Class Optical PCB Links Incorporating 360-Gb/s Bidirectional 850 nm Parallel Optical Transceivers

We report here on the design, fabrication, and characterization of highly integrated parallel optical transceivers designed for Tb/s-class module-to-module data transfer through polymer waveguides integrated into optical printed circuit boards (o-PCBs). The parallel optical transceiver is based on a through-silicon-via silicon carrier as the platform for integration of 24-channel vertical cavity surface-emitting laser and photodiode arrays with CMOS ICs. The Si carrier also includes optical vias (holes) for optical access to conventional surface-emitting 850 nm optoelectronic devices. The 48-channel 3-D transceiver optochips are flip-chip soldered to organic carriers to form transceiver optomodules. Fully functional optomodules with 24 transmitter + 24 receiver channels were assembled and characterized with transmitters operating up to 20 Gb/s/ch and receivers up to 15 Gb/s/ch. At 15 Gb/s, the 48-channel optomodules provide a bidirectional aggregate bandwidth of 360 Gb/s. In addition, o-PCBs have been developed using a 48-channel flex waveguide assembly attached to FR4 electronic boards. Incorporation of waveguide turning mirrors and lens arrays facilitates optical coupling to/from the o-PCB. Assembly of optomodules to the o-PCB using a ball grid array process provides both electrical and optical interconnections. An initial demonstration of the full module-to-module optical link achieved >; 20 bidirectional links at 10 Gb/s. At 15 Gb/s, operation at a bit error ratio of <; 10- 12 was demonstrated for 15 channels in each direction, realizing a record o-PCB link with a 225 Gb/s bidirectional aggregate data rate.

2.5D and 3D technology challenges and test vehicle demonstrations

Three-dimensional (3D) chip integration with through-silicon-vias (TSVs) can enable system benefits of enhanced performance, power efficiency, and cost reduction leveraging micro-architecture designs such as 2.5D silicon packages and 3D die stacks. 2.5D silicon packages and 3D die stacks structures integrated in modules each have unique technical challenges but each can provide system benefits including lower latency and higher bandwidth compared to traditional packaging solutions. Additional system benefits using 2.5D or 3D integration can include product miniaturization or increased function in the same size product. Leveraging proper design and micro-architecture for a system application, 3D technology can aide chip manufacturability for lower costs, sub-component heterogeneous integration, modular design and sub-component design reuse, which can reduce development expense and decrease time to market. 2.5D and 3D technology can reduce interconnection length between circuits leading to lower power consumption and lower latency as well as increase the number of interconnections which supports increased bandwidth to traditional 2D off chip interconnection. Appropriate design ground rules, clocking, and electrical models should match well defined technology attributes such as TSVs and silicon to silicon interconnection electrical parametrics. In addition a wafer test methodology for known good die (KGD) and high yield assembly integration approach are important to obtain integrated 2.5D and 3D modules. For complex 3D integration, proper consideration for module or integrated die stacked with TSVs and Si to Si interconnection may require redundancy and an integral repair methodology. 2.5D and 3D technology challenges may include an increase in the power delivery and cooling requirements to meet the increased circuit density and power density of these structures. For small, low power applications such as mobile devices, 2.5D and 3D technology can provide substantial benefit through both performance benefit and power savings and lead to longer battery life for the same function. For some high performance and high power applications, the 2.5D approach simplifies heterogeneous die integration without requiring leading to increases power density and heat removal cooling density. Whereas some high performance and high power applications using 3D technology may require extensive planning for power delivery with localized power regulation and specialized cooling approaches to avoid excessive in die stack temperatures while taking advantage of performance gains that these short links between heterogeneous die can provide. 3D die stacks using multi-core processors and wide I/O DRAM, eDRAM, SRAM or cache stacks can provide high bandwidth, performance improvements with lower latency. In addition to the power delivery and thermal challenges of 2.5D and 3D described above, there are 3D fabrication and industry compatibility challenges. Technology challenges include wafer integration and finishing with TSVs, test for known-good-die (KGD), assembly and module integration. Infrastructure compatibility and use of newly evolving industry standards such as Semi-3D standards for wafer handling and JEDEC standards for wide I/O memory to name two examples. Standards for wafer shipping are underway and other 3D compatibility standards are being defined over time. This research paper describes key challenges to enable systems using 2.5D and 3D technology. The paper also highlights progress and results for 2.5D and 3D hardware demonstrations and gives an outlook on future demonstrations.

Characterization of micro-bump C4 interconnects for Si-carrier SOP applications

This paper describes yield, contact resistance, and preliminary reliability test results on micro-bump C4 interconnects in modules containing Si-chips and Si-carriers. Modules containing eutectic PbSn or SnCu bump solders were fabricated with high yield, with similar interconnect contact resistances for both solders. The contact resistance and reliability test results to date suggest that reliable, high-current, high-density bump interconnections can be achieved for Si-carrier technology

3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections

In this paper a three-dimensional (3D) chip stacking technology using fine-pitched interconnects with lead-free solder is described. Different interconnect metallurgies such as Cu/Ni/In, Cu/In and Cu/Sn were considered and the bonding conditions to optimize the bonding parameters were determined. The effect of intermetallic compound (IMC) formation on the mechanical properties of the joins is discussed. Unlike standard 100-micron C4 solder balls, very small solder volumes (< 6 microns high) were investigated. The mechanical properties were evaluated by shear and impact shock testing, while scanning electron microscopy (SEM) and optical microscopy were used to study the morphology of the IMC layers in solder joins before and after annealing. It was found that Cu/Ni/In and Cu/In interconnections have slightly lower shear strength per bump. While these values were lower than the Cu/Sn joins, the Cu/Ni/In chips passed the impact shock test for a simulated heat sink mass of 27 g/cm2. The reasons for the differences in reliability of these metallurgies are discussed. 3D chip stacking using two-layers of chips with fine-pitch lead-free interconnects was demonstrated. The resistance of link chains comprising through-vias, lead-free interconnects and Cu links were measured using a 4-point probing method. The average resistance of the through-via including the lead-free interconnect was 21 mOmega.