Zhiliang Xia

Comprehensive modeling of NAND flash memory reliability: Endurance and data retention

A reliability modeling solution including endurance and data retention is developed for NAND Floating Gate Flash memory. Endurance model with trap generation considers the tunneling oxide quality distribution with process effect. Electric field and tunneling current effect also have been included. The complicated trap effect on threshold voltage and Swing shift is well explained based on non-uniformly trapped charge distribution. Thermal emission with Poole-Frenkel model and tunneling from trap to substrate are included for data retention simulation. Dominant mechanisms under high and low temperature are discussed. Broaden phenomenon of threshold voltage distribution after high temperature data retention is modeled and demonstrated based on random trap variation in tunneling Oxide.

Gate-Induced Image Force Barrier Lowering in Schottky Barrier FETs

In this paper, we analyze the gate-induced image force barrier lowering in a 45-nm-gate-length ultra-thin-body silicon-on-insulator structure by using 2D full-band self-consistent ensemble Monte Carlo simulation with both tunneling current and thermal emission current. Results show that gate-induced barrier lowering has a very significant influence on the drive current. The influence of gate voltage, Schottky barrier height, spacer and channel doping concentration is also investigated and a theoretical analysis is presented.

Anomalous Negative Bias Temperature Instability Degradation Induced by Source/Drain Bias in Nanoscale PMOS Devices

The effect of source/drain (S/D) bias on the negative bias temperature instability (NBTI) of pMOSFETs is studied. The anomalously enhanced NBTI under S/D bias conditions is observed, which cannot be explained by the conventional reaction-diffusion model. A new mechanism based on the enhanced interfacial dissociation of equivSi-H bonds induced by the energetic holes (the hole energy Eh is higher than the reaction activation energy Ea of equivSi-H bond dissociation) is proposed to address the observed degradation behaviors. Monte Carlo simulations are used to identify the validity of the new mechanism.

An Analytical Potential Model of Double-Gate MOSFETs with Schottky Source/Drain

A two-dimensional (2D) analytical model of double-gate (DG) MOSFETs with Schottky source/drain(S/D) is developed based on solving Poisson equation. We calculated the 2D potential distribution in the channel. An expression for threshold voltage for short-channel DG MOSFETs with Schottky S/D is also presented by defining the turning on condition. The results of the model are verified by numerical simulator, DESSIS 8.0

Evaluating the effects of physical mechanisms on the program, erase and retention in the charge trapping memory

In this work, a new efficient simulation method with comprehensive physical models is developed to evaluate the performance of CTM at various biases, temperatures, and gate stack configurations. The dominant physical mechanisms on the P/E/R operations of CTM are clarified.

Characteristics of different structure sub-100nm MOSFETs with high-k gate dielectrics

The extensive simulations are carried out to study impact of high K dielectric both on the channel and the source/drain extension region of a typical 70nm MOSFET by the two dimensional device simulator ISE. The key factors affecting the device characteristics are investigated. The different structures of high K gate dielectric MOSFETs including SOI MOSFET and recess channel MOSFET are also simulated.

Monte Carlo Simulation of Band-to-Band Tunneling in Silicon Devices

A band-to-band tunneling model including trap-assisted tunneling has been implemented in our ensemble full band Monte Carlo simulator. Four kinds of band-to-band tunneling mechanisms are taken into account. All the parameters in the band-to-band tunneling model are verified by comparing the pn junction reverse current with the experimental data. Then, gate-induced-drain-leakage currents caused by band-to-band tunneling in a 45 nm gate length n-metal–oxide–semiconductor field-effect-transistor are investigated. Results indicate that band-to-band tunneling can cause additional hot holes which becomes an important issue for the device reliability. Moreover, The gate-induced-drain-leakage currents caused by band-to-band tunneling in parallel with Si/SiO2 interface and normal to Si/SiO2 interface are compared. The influence of drain voltage on the two components of the gate-induced-drain-leakage currents is considered.

Simulation of flash memory including charge trapping and de-trapping by Monte Carlo method

We propose a self-consistent method to simulate charge trapping and de-trapping in charge storage layer and its interfaces of SONOS type flash memory devices. This method can be used under various applied voltages; in various structures composed of multiple material, thickness and shape of gate stack layers. It can also work with arbitrary trap density distribution in either real space or energy space. Further more, the self-consistent method has enough flexibility to accommodate detailed physical models

Novel Schottky barrier MOSFET with dual-layer silicide source/drain structure

An n-channel Schottky barrier MOSFET with dual-layer silicide source/drain (DS-SB-MOSFET) has been proposed for nanoscale application. In this device, the stacked source and drain of SB-MOSFET are composed with two metal silicide layers. The Schottky barrier height of the top silicide/channel contact is lower than that of the bottom silicide/channel contact. The low Schottky barrier height of top silicide/channel contact near the gate oxide improves the electron injection capability in on-state. And the high Schottky barrier height of the bottom silicide/channel contact below the top silicide layer reduces the leakage current in off-state. Simulations indicated that the performance of DS-SB-MOSFET has been significantly improved, compared with that of the conventional Schottky barrier MOSFET (SB-MOSFET).

Investigation of RF Performance of Nano-Scale Ultra-Thin-Body Schottky-Barrier MOSFETs Using Monte Carlo Simulation

A Monte Carlo investigation of the dynamic performance of nano-scale ultra-thin-body (UTB) Schottky-Barrier MOSFETs (SB-MOSFETs) is presented. A thorough account of how the gate voltage and SB barrier height affect the RF performance of UTB SB-MOSFETs is elaborated. The UTB SB-MOSFET offers excellent RF performance with high values of fTand fmax. The peak fTis higher than 600 GHz with SB height ranging from 0.2eV to 0.3eV. It is found that gate voltage has a significant influence on fTand fmaxof UTB SB-MOSFETs whereas the barrier height is of minor importance. However, both gate voltage and SB height affect the gmand gdsobviously. For high performance of UTB SB-MOSFETs, appropriate gate voltage and SB height is of great importance.