Shun-Meen Kuo

Electromigration of eutectic SnPb solder interconnects for flip chip technology

The electromigration of eutectic SnPb solder interconnects between a Si chip and a FR4 substrate was studied at 120 °C for up to 324 h with current stressing of 104 amp/cm2. Hillocks were observed at the anode and voids at the cathode. The dominant diffusing species was found to be Pb, confirmed by its accumulation at the anode. Diffusion markers were used to measure the electromigration flux and calculate the effective charge of atomic diffusion in the solder. Extensive microstructural evolution was also observed in the two-phase solder alloy that occurred by a ripening process.

Impact of flip-chip packaging on copper/low-k structures

Copper/low-k structures are the desired choice for advanced integrated circuits (ICs). Nevertheless, the reliability might become a concern due to the considerably lower strength and greater coefficient of thermal expansion (CTE) of the low-k materials. To ensure successful integration of the new chips within advanced packaging products, it is essential to understand the impact of packaging on chips with copper/low k structures. In this study, flip-chip die attach process has been studied. Multilevel, multiscale modeling technique was used to bridge the large gap between the maximum and minimum dimensions. Interface fracture mechanics-based approach has been used to predict interface delamination. Both plastic ball grid array (PBGA) and ceramic ball grid array (CBGA) packages were evaluated. Critical failure locations and interfaces were identified for both packages. The impact of thin film residual stresses has been studied at both wafer level and package level. Both PBGA and CBGA packaging die-attach processes induce significantly higher crack driving force on the low-k interfaces than the wafer process. CBGA die-attach might be more critical than PBGA die-attach due to the higher temperature. During CBGA die-attach process, the crack driving force at the low-k/passivation interface may exceed the measured interfacial strength. Two solutions have been suggested to prevent catastrophic delamination in copper/low-k flip-chip packages, improving adhesion strength of low-k/barrier interface or adding tiles and slots in low-k structures to reduce possible area for crack growth.

Mechanics-based solutions to RF MEMS switch stiction problem

RF micro-electro-mechanical systems (MEMS) switches are an attractive solution to switch antenna bands and transmit/receive switching for future multiband, high bandwidth cell phones. However, Stiction is a major concern for resistive switches with metal-to-metal contact. An iterative-coupled electrostatic-structural analysis is utilized to evaluate the effect of design parameters on restoring force of MEMS switches. Parameters including metal thickness, dielectric thickness, beam-to-ground gap height, metal and dielectric width, and cantilever beam length can be evaluated. The electrostatic force is first calculated based on the electrical field component. A structural analysis is then performed to determine the cantilever beam deflection due to the electrostatic force. A unique integrated empirical-numerical method is used to quantitatively determine the stiction force based on measured actuation voltages for real devices. The analysis can provide quick evaluation and screenings of proposed designs to determine if their actuation voltage falls in the acceptable range. Simulation prediction agrees very well with test measurements. Although increasing cantilever thickness and shortening cantilever length both increase restoring force, the actuation voltage will increase significantly as a result. The most favorable modification is to increase the electrode area. A short and wide structure with a large area can increase restoring force while maintaining low actuation voltage. Compared to similar bi-layer designs, sandwich designs can be actuated at further reduced voltages without changing the beam restoring force. In addition, the sandwich structure, being thermal-stress-balanced, is less sensitive to temperature excursion. With the properly selected design parameters, the new designs will be able to achieve the break away restoring force of the original design at much lower actuation voltages. Switches with good electrical as well as mechanical performances have been successfully fabricated.

A simulation method for predicting packaging mechanical reliability with low /spl kappa/ dielectrics

It is essential to understand the impact of packaging on chips with copper/low k structures. In this paper, a multi-level, multi-scale modeling technique is used to study the die attach process. Four-level models are built to analyze the packaging impact on the wafer-level behavior. An interface fracture mechanics-based approach is adopted to predict interface delamination. The impact of thin film residual stresses is studied at both the wafer level and package level. Both Plastic Ball Grid Array (PBGA) and Ceramic Ball Grid Array (CBGA) packages are evaluated. Critical failure locations and interfaces are identified for both packages. Two solutions are suggested to prevent catastrophic delamination in copper low-k flip-chip packages.

Motorola MEMS switch technology for high frequency applications

Motorola Semiconductor Products Sector (SPS) has made significant progress in developing an integrated MEMS switch network for use in next-generation portable wireless systems. This MEMS switch technology has significantly better RF characteristics than conventional PIN diodes or FET switches and consumes less power. The RF MEMS switch exhibits insertion loss under 0.3 dB, isolation greater than 50 dB, and operating power under 200 /spl mu/W. The RF MEMS switch chip is integrated with a high voltage charge pump plus control logic chips into a single package that provides a network system to accommodate low voltage requirements in portable wireless applications.

Analysis of RF MEMS switch packaging Process for yield improvement

Radio frequency microelectro-mechanical systems (RF MEMS) switches offer significant performance advantages in high-frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320degC. The assembled packages were then attached to a printed circuit board at 220degC. During the process, some switches failed due to electrical shorting. Interestingly, more failures were observed at the lower temperature of 220degC rather than 320degC. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance

Stress/strength and reliability evaluations on UBM in different solder systems

UBM (Under Bump Metallurgy) reliability is one of the critical issues in the total reliability of a flip-chip bumping technology. Since the UBM materials and structures vary for different bumping technologies, the UBM strength and reliability need to be determined for each design and process. In addition, the stress that a UBM experiences during thermal cycles depends on the solder alloy used in the interconnect. Different solder alloys require different UBM structures and strengths to achieve good reliability thermal cycling. In this study, a simplified stress model is developed to determine the UBM stress during thermal cycling. A simplified stress model for the UBM strength is also developed. These models are used to predict the stress and strength of the UBM under the die pull test and the thermal cycle conditions for both eutectic and high lead solder systems. A methodology for using the pull test results to evaluate UBM reliability is also discussed. This methodology can be extended to the studies of UBMs with other solder systems.

Process-Induced Thermal Effect on Packaging Yield of RF MEMS Switches

RF MEMS switches offer significant performance advantages in high frequency RF applications. The switches are actuated by electrostatic force when voltage was applied to the electrodes. Such devices provide high isolation when open and low contact resistance when closed. However, during the packaging process, there are various possible failure modes that may affect the switch yield and performance. The RF MEMS switches were first placed in a package and went through lid seal at 320°C. The assembled packages were then attached to a printed circuit board at 220°C. During the process, some switches failed due to electrical shorting. More interestingly, more failures were observed at the lower temperature of 220°C rather than 320°C. The failure mode was associated with the shorting bar and the cantilever design. Finite element simulations and simplified analytical solutions were used to understand the mechanics driving the behaviors. Simulation results have shown excellent agreement with experimental observations and measurements. Various solutions in package configurations were explored to overcome the hurdles in MEMS packaging and achieve better yield and performance.© 2002 ASME

RF MEMS Switch Heat Dissipation in Discrete and Wafer-Level MEMS Packages

In discrete RF (Radio Frequency) MEMS (MicroElectroMechanical Systems) packages, MEMS devices were fabricated on Silicon or GaAs (Galium Arsenide) chips. The chips were then attached to substrates with die attach materials. In wafer-level MEMS packages, the switches were manufactured directly on substrates. For both types of packages, when the switches close, a contact resistance of approximately 1 Ohm exists at the contact area. As a result, during switch operations, a considerable amount of heat is generated in the minuscule contact area. The power density at the contact area could be up to 1000 times higher than that of typical power amplifiers. The high power density may overheat the contact area, therefore affect switch performance and jeopardize long-term switch reliabilities. In this paper, thermal analysis was performed to study the heat dissipation at the switch contact area. The goal is to control the “hot spots” and lower the maximum junction temperature at the contact area. A variety of chip materials, including Silicon, GaAs have been evaluated for the discrete packages. For each chip material, the effect of die attach materials was considered. For the wafer-level packages, various substrate materials, such as ceramic, glass, and LTCC (Low-Temperature Cofire Ceramic) were studied. Thermal experiments were conducted to measure the temperature at the contact area and its vicinity as a function of DC and RF powers. Several solutions in material selection and package configurations were explored to enable the use of MEMS with chips or substrates with relatively poor thermal conductivity.© 2002 ASME