Lei Shen

Ultrafast pulse characterization of hot carrier injection effects on ballistic carrier transport for sub-100 nm MOSFETs

In this work, we investigate the effect of hot carrier injection (HCI) on the ballistic transport characteristics of SOI MOSFETs for the first time. Ballistic efficiency is an important indicator of device performance for nanoscale transistors. In the process of HCI stress, the traps and defects generated in the transistor channel would increase the carrier scattering and therefore degrade the ballistic efficiency. The effect of this degradation changes with gate length. In addition, due to low thermal conductivity of the oxide layer and high on-state current for nanoscale transistors, the SOI MOSFETs suffer from severe self-heating effect (SHE) which would affect the accurate evaluation of HCI effects on the ballistic carrier transport. Ultrafast pulse measurement were employed in this study to exempt the SHE from the characterization process, yielding more realistic results for the reliability estimation on device ballisticity.

Impact of self-heating effects on nanoscale Ge p-channel FinFETs with Si substrate

In this paper, self-heating effects (SHE) in nanoscale Ge p-channel FinFETs with Si substrate are evaluated by TCAD simulation. Hydrodynamic transport with modified mobilities and Fourier´s law of heat conduction with modified thermal conductivities are used in the simulation. Ge p-channel single-fin FinFET devices with different S/D extension lengths and fin heights, and multi-fin FinFETs with different fin numbers and fin pitches are successively investigated. Boundary thermal resistances at source, drain and gate contacts are set to 2000 μm2K/W and the substrate thermal boundary condition is set to 300 K so that the source and drain heat dissipation paths are the first two heat dissipation paths. The results are listed below: (i) 14 nm Ge p-channel single-fin FinFETs with a 47 nm fin pitch experience 9.7% on-state current degradation. (ii) Considering the same input power, FinFETs with a longer S/D extension length show a higher lattice temperature and a larger on-state current degradation. (iii) Considering the same input power, FinFETs with a taller fin height show a higher lattice temperature. (iv) The temperature in multi-fin FinFET devices will first increase then saturate with the increasing fin number. At last, thermal resistances in Ge p-channel single-fin FinFETs and multi-fin FinFETs are investigated.

Calibration of drift-diffusion model in quasi-ballistic transport region for FinFETs

In the past few years, conventional digital IC technologies have developed rapidly and the device structures have shrunk down to the quasi-ballistic region which strongly affects the device characteristics. The usage of the steady-state transport model and the parameters of the drift-diffusion (DD) method may not correctly model the performance of these devices, including the velocity distributions of the carriers. Several previous studies have suggested modifying the transport parameters of the DD model to continue using it in the quasi-ballistic region. In this paper, a Monte Carlo (MC) simulator is used to calibrate the transport parameters of the DD model for silicon FinFETs. The device features obtained via the parameter-calibrated DD model fit well with the MC simulator. The trends of the calibration factors are also investigated for varying drain voltage, gate voltage, fin width and gate length.

Impact of crystal orientation and surface scattering on DG-MOSFETs in quasi-ballistic region

The characteristics of nano scale n-type double gate MOSFETs with (100) and (110) surfaces are studied using 3D full band ensemble Monte Carlo simulator. The anisotropic surface scattering mechanism is investigated. The (100) case is sensitive to the gate voltage more than the (110) case. The impact of crystal orientation and surface scattering on transport features mainly reflects in the carrier velocity distribution. The electron transport features with (100) direction are greater than that with (110) direction, but are more likely to be affected by the surface scattering.

Unified self-heating effect model for advanced digital and analog technology and thermal-aware lifetime prediction methodology

Self-heating effect (SHE) has become a significant concern for device performance, variability and reliability co-optimization due to more confined layout geometry and lower-thermal-conductivity materials adopted in advanced transistor technology, which substantially impacts the integrated circuit (IC)s design schemes. In this work, a new methodology for evaluation of SHE in both digital and analog circuits is demonstrated by using pulse-aware and existing sine-aware analytical models respectively. Correlating SHE to physics-based thermal-aware reliability models provides insights for design and sign-offs of advanced digital and analog ICs.

Investigation of local heating effect for 14nm Ge pFinFETs based on Monte Carlo method

FinFET is regarded as one of the most promising device structure for future scaling-down demands. However, heat dispassion is a severe problem for the device performance and reliability in nano-scale FinFETs. Germanium (Ge) is a novel channel material with its high carrier mobility, especially for PMOSFET. However, the bulk thermal conductivity of Ge (52.98Wm-1K-1) is almost 3 times smaller than that of Si (148.6Wm-1K-1)[1], which will lead to more serious heat dispassion problems in Ge devices. Whats more, the phonon mean free path is largely decreased in nano-device structure due to increased surface scatterings, which leads to a largely reduced thermal conductivity. Hence, heat dissipation problems will have a large impact on the performance of Ge FinFETs. In this paper, we use 3D Full Band Self-consistent Ensemble Monte Carlo Simulator and 3D Fourier Heat Conduction Solver to study the local heating effects (LHE) and its impact on 14nm Ge SOI pFinFETs. The heat dissipation path is also evaluated. From the simulation results, we find that 14nm Ge SOI FinFETs will experience severe heating problems and heat effects will seriously affect the device performance.

Investigation of scattering mechanism in nano-scale double gate In 0.53 Ga 0.47 As nMOSFETs by a deterministic BTE solver

We investigate the scattering mechanism in ultrashort double gate In0.53Ga0.47As nMOSFETs by deterministically solving Boltzmann transport equation (BTE). The intra-valley acoustic phonon scattering, optical phonon scattering, intervalley optical scattering, polar optical scattering, and surface roughness (SR) scattering are considered. The impacts of scattering on the performance of device under high/low biases are compared. Results show that the ballistic ratio (Iscat/Iball) decreases from 96.8% to 94.5% when the drain bias increases from 0.05V to 0.6V, which is mainly caused by the inter-valley scatterings.