Li-Wen Chang

Flexible Control of Block Copolymer Directed Self‐Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning

www.MaterialsViews.com C O M M U N IC A IO N He Yi , Xin-Yu Bao , Jie Zhang , Christopher Bencher , Li-Wen Chang , Xiangyu Chen , Richard Tiberio , James Conway , Huixiong Dai , Yongmei Chen , Subhasish Mitra , and H.-S. Philip Wong * Flexible Control of Block Copolymer Directed SelfAssembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning

Experimental demonstration of aperiodic patterns of directed self-assembly by block copolymer lithography for random logic circuit layout

We have experimentally demonstrated block copolymer lithography in conjunction with optical lithography features on dimensional scales close to the natural pitch of the self-assembling block copolymer. Within this context, the inherent self-assembled shape, size and arrangement will self-adjust to accommodate the external confinement. This added flexibility of directed self-assembly of aperiodic patterns can potentially be used for patterning contact holes for random logic circuit layout.

Diblock copolymer directed self-assembly for CMOS device fabrication

We present our recent work on using diblock copolymer directed self-assembly for the fabrication of silicon MOSFETs. Instead of using self-assembly to assemble the entire device, we plan to utilize self-assembly to perform one critical step of the complex MOSFET process flow in the beginning. Initial results of using PS-b-PMMA to define pores with hexagonal array having diameter of 20 nm for contact hole patterning will be described. Potential integration issues for making MOSFETs will also be addressed.

Contact-hole patterning for random logic circuits using block copolymer directed self-assembly

Block copolymer directed self-assembly (DSA) is a promising extension of optical lithography for device fabrication akin to double-patterning. The irregular distribution of contact holes in circuit layouts is one of the biggest challenges for DSA patterning because the self-assembly tends to form regular patterns naturally. Although the small guiding templates are shown to guide the self-assembly off the natural geometry by strong boundary confinement [1, 2] (Fig. 1), it is insufficient to simply surround contact holes with guiding templates without optimizing the placement and geometry of the guiding templates.

Block copolymer directed self-assembly enables sublithographic patterning for device fabrication

The use of block copolymer self-assembly for device fabrication in the semiconductor industry has been envisioned for over a decade. Early works by the groups of Hawker, Russell, and Nealey [1-2] have shown a high degree of dimensional control of the self-assembled features over large areas with high degree of ordering. The exquisite dimensional control at nanometer-scale feature sizes is one of the most attractive properties of block copolymer self-assembly. At the same time, device and circuit fabrication for the semiconductor industry requires accurate placement of desired features at irregular positions on the chip. The need to coax the self-assembled features into circuit layout friendly location is a roadblock for introducing self-assembly into semiconductor manufacturing. Directed self-assembly (DSA) and the use of topography to direct the self-assembly (graphoepitaxy) have shown great promise in solving the placement problem [3-4]. In this paper, we review recent progress in using block copolymer directed self-assembly for patterning sub-20 nm contact holes for practical circuits.

SRAM, NAND, DRAM contact hole patterning using block copolymer directed self-assembly guided by small topographical templates

Sublithographic patterning using Directed Self-Assembly (DSA) is demonstrated for practical circuits with non-periodic features. The DSA of irregularly distributed contact holes is guided by small topographical templates patterned by immersion 193 nm optical lithography. We experimentally demonstrate flexible and precise DSA control of 25 nm contact holes (centroid deviation∼1 nm) guided by 66 nm guiding templates for industry-standard 22-nm SRAM cells. Solution are also proposed to pattern contact holes (CD∼15 nm, Pitch∼40 nm, σ∼2 nm) for 15-nm NAND with two-hole templates and 2×-nm DRAM with three-hole templates. DSA is a low-cost, high-throughput extension of the double-patterning technique.

Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.

Mandrel-based patterning: density multiplication techniques for 15nm nodes

In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of using lithography as the principal process for generating device features, the role of lithography becomes to generate a mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to the scaling roadmap as the exposure tools themselves. Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash where layouts were simple and design space was focused. But today, the use of advanced automated decomposition tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails formed onto the substrate. In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of EUV+SADP.

Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-k/metal gate) reach their limits. By carefully engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of device footprint and device structure scaling that will enable technology scaling for several generations beyond the currently perceived limits.

Top-gated FETs/inverters with diblock copolymer self-assembled 20 nm contact holes

We have fabricated FETs and CMOS inverters with 20 nm contact holes patterned using self-assembled diblock copolymer. Alignment of the self-assembled contact holes to the MOSFET source and drain is achieved with a guiding layer. The self-assembly process is integrated with an existing CMOS process flow using conventional tools on a full wafer level. This is the first demonstration of functional circuits fabricated using self-assembly at the (n+1)th patterning level where n ≥ 1.