Li Zehong

Above 700 V superjunction MOSFETs fabricated by deep trench etching and epitaxial growth

Silicon superjunction power MOSFETs were fabricated with deep trench etching and epitaxial growth, based on the process platform of the Shanghai Hua Hong NEC Electronics Company Limited. The breakdown voltages of the fabricated superjunction MOSFETs are above 700 V and agree with the simulation. The dynamic characteristics, especially reverse diode characteristics, are equivalent or even superior to foreign counterparts.

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) with buried p-layer (BP) is proposed in this paper. Since the negative charges in the BP layer modulate the bulk electric field distribution, the electric field peaks both at the junction of the p base/n-type carrier stored (N-CS) layer and the corners of the trench gates are reduced, and new electric field peaks appear at the junction of the BP layer/N− drift region. As a result, the overall electric field in the N− drift region is enhanced and the proposed structure improves the breakdown voltage (BV) significantly compared with the LPT CSTBT. Furthermore, the proposed structure breaks the limitation of the doping concentration of the N—CS layer (NN—CS) to the BV, and hence a higher NN—CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop (Vce(sat)) can be obtained with almost constant BV. The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm−3, a thickness of LBP = 2.5 μm, and a width of WBP = 5 μm, the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V, with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3. However, with the same N−-drift region thickness of 150 μm and NN—CS, the BV of the CSTBT decreases from 1598 V to 247 V. Meanwhile, the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3.

Insulated gate bipolar transistor with trench gate structure of accumulation channel

An accumulation channel trench gate insulated gate bipolar transistor (ACT-IGBT) is proposed. The simulation results show that for a blocking capability of 1200 V, the on-state voltage drops of ACT-IGBT are 1.5 and 2 V at a temperature of 300 and 400 K, respectively, at a collector current density of 100 A/cm2. In contrast, the on-state voltage drops of a conventional trench gate IGBT (CT-IGBT) are 1.7 and 2.4 V at a temperature of 300 and 400 K, respectively. Compared to the CT-IGBT, the ACT-IGBT has a lower on-state voltage drop and a larger forward bias safe operating area. Meanwhile, the forward blocking characteristics and turn-off performance of the ACT-IGBT are also analyzed.

Carrier stored trench-gate bipolar transistor with p-floating layer

A carrier stored trench-gate bipolar transistor (CSTBT) with a p-floating layer (PF-CSTBT) is proposed. Due to the p-floating layer, the thick and highly doped carrier stored layer can be induced, and the conductivity modulation effect will be enhanced near the emitter. The accumulation resistance and the spreading resistance are reduced. The on-state loss will be much lower than in a conventional CSTBT. With the p-floating layer, the distribution of electric fields of the conventional IGBT is reformed, and the breakdown voltage is remarkably improved. The simulation results have shown that the forward voltage drop (VCE–on) of the novel structure is reduced by 20% and 17% respectively, compared with the conventional trench IGBT (TIGBT) and CSTBT under the same conditions. Moreover, an increment of more than 100 V of the breakdown voltage is achieved without sacrificing the SCSOA (short circuit safely operation area) compared with the conventional TIGBT.

Novel lateral IGBT with n-region controlled anode on SOI substrate

A new lateral insulated-gate bipolar transistor (LIGBT) structure on SOI substrate, called an n-region controlled anode LIGBT (NCA-LIGBT), is proposed and discussed. The n-region controlled anode concept results in fast switch speeds, efficient area usage and effective suppression NDR in forward I–V characteristics. Simulation results of the key parameters (n-region doping concentration, length, thickness and p-base doping concentration) show that the NCA-LIGBT has a good tradeoff between turn-off time and on-state voltage drop. The proposed LIGBT is a novel device for power ICs such as PDP scan driver ICs.

Analysis of the dV/dt effect on an IGBT gate circuit in IPM

The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV/dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV/dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on. By optimizing these parameters, the dV/dt induced voltage spike can be effectively controlled.

A new short-anoded IGBT with high emission efficiency

A novel short-anoded insulated-gate bipolar transistor (SA-IGBT) with double emitters is proposed. At the on-state, the new structure shows extraordinarily high emission efficiency. Moreover, with a short-contacted anode, it further enhances the hole emission efficiency because of the crowding of the electrons. The forward voltage drop VF of this structure is 1.74 V at a current density 100 of A/cm2. Compared to the conventional NPT IGBT (1.94 V), segment-anode IGBT (SA-NPN 2.1 V), and conventional SA-IGBT (2.33 V), VF decreased by 10%, 17% and 30%, respectively. Furthermore, no NDR has been detected comparing to the SA-IGBT. At the off-state, there is a channel for extracting excessive carriers in the drift region. The turn-off loss Eoff of this proposed structure is 8.64 mJ/cm2. Compared to the conventional NPT IGBT (15.3 mJ/cm2), SA-NPN IGBT (12.8 mJ/cm2), and SA-IGBT (12.1 mJ/cm2), Eoff decreased by 43.7%, 32% and 28%, respectively.

Trench gate IGBT structure with floating P region

A new trench gate IGBT structure with a floating P region is proposed, which introduces a floating P region into the trench accumulation layer controlled IGBT (TAC-IGBT). The new structure maintains a low on-state voltage drop and large forward biased safe operating area (FBSOA) of the TAC-IGBT structure while reduces the leakage current and improves the breakdown voltage. In addition, it enlarges the short circuit safe operating area (SCSOA) of the TAC-IGBT, and is simple in fabrication and design. Simulation results indicate that, for IGBT structures with a breakdown voltage of 1200 V, the leakage current of the new trench gate IGBT structure is one order of magnitude lower than the TAC-IGBT structure and the breakdown voltage is 150 V higher than the TAC-IGBT.

A snapback suppressed reverse-conducting IGBT with uniform temperature distribution

A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring a floating P-plug is proposed. The P-plug is embedded in the n-buffer layer to obstruct the electron current from flowing directly to the n-collector, which achieves the hole emission from the p-collector at a small collector size and suppresses the snapback effectively. Moreover, the current is uniformly distributed in the whole wafer at both IGBT mode and diode mode, which ensures the high temperature reliability of the RC-IGBT. Additionally, the P-plug acts as the base of the N-buffer/P-float/N-buffer transistor, which can be activated to extract the excessive carriers at the turn-off process. As the the simulation results show, for the proposed RC-IGBT, it achieves almost snapback-free output characteristics with a uniform current density and a uniform temperature distribution, which can greatly increase the reliability of the device.

A novel superjunction MOSFET with improved ruggedness under unclamped inductive switching

The ruggedness of a superjunction metal—oxide semiconductor field-effect transistor (MOSFET) under unclamped inductive switching conditions is improved by optimizing the avalanche current path. Inserting a P-island with relatively high doping concentration into the P-column, the avalanche breakdown point is localized. In addition, a trench type P+ contact is designed to shorten the current path. As a consequence, the avalanche current path is located away from the N+ source/P-body junction and the activation of the parasitic transistor can be effectively avoided. To verify the proposed structural mechanism, a two-dimensional (2D) numerical simulation is performed to describe its static and on-state avalanche behaviours, and a method of mixed-mode device and circuit simulation is used to predict its performances under realistic unclamped inductive switching. Simulation shows that the proposed structure can endure a remarkably higher avalanche energy compared with a conventional superjunction MOSFET.