Li Zhenrong

A 2.4 GHz high-linearity low-phase-noise CMOS LC-VCO based on capacitance compensation

A 2.4 GHz high-linearity low-phase-noise cross-coupled CMOS LC voltage-controlled oscillator (VCO) is implemented in standard 0.18-μm CMOS technology. An equalization structure for tuning sensitivity base on the three-stage distributed biased switched-varactor bank and the differential switched-capacitor bank is adopted to reduce the variations of the VCO gain, achieve high linearity, and optimize the phase-noise performance. Compared to the conventional VCO, the proposed VCO has more constant gain over the entire tuning range. The tuning range is about 18.7% from 2.23 to 2.69 GHz, and the phase noise is −95 dBc/Hz at 100-kHz offset and −117 dBc/Hz at 1-MHz offset from the carrier frequency of 2.42 GHz. The power dissipation is 2.1 mW from a 1.8 V power supply. The active area of this VCO is 500 × 810 μm2.

The Effects of the Poling Conditions on Dielectric and Piezoelectric Properties of Pb(In1/2Nb1/2)O3-Pb(Mg1/3Nb2/3)O3-PbTiO3 Single Crystals with Morphotropic Phase Boundary Composition

Dielectric and piezoelectric properties of Pb(In1/2Nb1/2)O3-Pb(Mg1/3Nb2/3)O3-PbTiO3 single crystals with morphotropic phase boundary composition under different poling conditions were investigated. The orthorhombic to tetragonal phase transition temperature for high temperature poled 0.24PIN-0.42PMN-0.33PT single crystal occurs ∼70°C, ∼30°C less than that poled under room temperature poling condition with electric field 10kV/cm, which limit its application in high temperature environments. Rhombohedral to tetragonal phase transition temperature is nearly same for 0.24PIN-0.46PMN-0.30PT single crystal poled under different conditions. The tetragonal to cubic phase transition temperature is unchanged no matter whether the crystal is poled at high temperature or at room temperature.

Design of a 0.18 μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band. A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section, which mainly consists of a low noise amplifier (LNA), a down-converter, polyphase filters and summing circuits. An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage. Also, a re-designed wideband double balance mixer is implemented in the down conversion stage, which provides better gain, noise figure and linearity performances. Using a TSMC 0.18 μm 1P4M RF CMOS process, a compact 1.27 GHz/1.575 GHz dual-band GNSS frontend is realized in the proposed low-IF topology. The measurements exhibit the gains of 45 dB and 43 dB, and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands, respectively. The frontend model consumes about 11.8–13.5 mA current on a 1.8 V power supply. The core occupies 1.91 × 0.53 mm2 while the total die area with ESD is 2.45 × 2.36 mm2.

A 9.8-mW 1.2-GHz CMOS frequency synthesizer with a low phase-noise LC-VCO and an I/Q frequency divider

A 1.2 GHz frequency synthesizer integrated in a RF receiver for Beidou navigation is implemented in standard 0.18 μm CMOS technology. A distributed biased varactor LC voltage-controlled oscillator is employed to achieve low tuning sensitivity and optimized phase noise performance. A high-speed and low-switching-noise divider-by-2 circuit based on a source-coupled logic structure is adopted to generate a quadrature (I/Q) local oscillating signal. A high-speed 8/9 dual-modulus prescaler (DMP), a programmable-delay phase frequency detector without dead-zone problem, and a programmable-current charge pump are also integrated into the frequency synthesizer. The frequency synthesizer demonstrates an output frequency from 1.05 to 1.30 GHz, and the phase noise is −98.53 dBc/Hz at 100-kHz offset and −121.92 dBc/Hz at 1-MHz offset from the carrier frequency of 1.21 GHz. The power dissipation of the core circuits without the output buffer is 9.8 mW from a 1.8 V power supply. The total area of the receiver is 2.4 × 1.6 mm2.

A 0.18 μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5–1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.

Morphology and Characterization of GaN Crystals Grown by Na Flux Method under 7 MPa Nitrogen Pressure

A large number of GaN pyramid shaped crystals with the maximum size of about 3 mm have been grown by Na flux method. The morphologies of GaN crystals were observed with optical microscope and scanning electron microscope (SEM). The quality of GaN crystal was checked by X-ray powder diffraction (XRD) and photoluminescence (PL) spectra. The SEM photographs show most of the crystals were hexagonal pyramidal, and there were a considerable number of hexagonal bipyramidal GaN crystals with twin plane. The relationships between GaN crystal morphology and the growth rate were also discussed.

A 0.18 μm CMOS single-inductor single-stage quadrature frontend for GNSS receiver

This paper presents an improved merged architecture for a low-IF GNSS receiver frontend, where the bias current and functions are reused in a stacked quadrature LNA-mixer-VCO. Only a single spiral inductor is implemented for the LC resonator and an extra 1/2 frequency divider is added as the quadrature LO signal generator. The details of the design are presented. The gain plan and noise figure are discussed. The phase noise, quadrature accuracy and power consumption are improved. The test chip is fabricated though a 0.18 ?m RF CMOS process. The measured noise figure is 5.4 dB on average, with a gain of 43 dB and a IIP3 of ?39 dBm. The measured phase noise is better than ?105 dBc/Hz at 1 MHz offset. The total power consumption is 19.8 mW with a 1.8 V supply. The experimental results satisfy the requirements for GNSS applications.