Liam Floyd

Low-temperature electron mobility in Trigate SOI MOSFETs

Evidence of one-dimensional subband formation is found at low temperature in trigate silicon-on-insulator MOSFETs, resulting in oscillations of the I/sub D/(V/sub G/) characteristics. These oscillations correspond to the filling of energy subbands by electrons as the gate voltage is increased. High mobility, reaching 1200 cm/sup 2//Vs, is measured in the subbands at T=4.4 K. Subband mobility decreases as temperature is increased. Conduction in subbands disappears for temperatures higher than 100 K or for drain voltage values that are significantly larger than kT/q.

Temperature effects on trigate SOI MOSFETs

Trigate silicon-on-insulator (SOI) MOSFETs have been measured in the 5-400 K temperature range. The device fin width and height is 45 and 82 nm, respectively, and the p-type doping concentration in the channel is 6/spl times/10/sup 17/ cm/sup -3/. The subthreshold slope varies linearly with temperature as predicted by fully depleted SOI MOS theory. The mobility is phonon limited for temperatures larger than 100 K, while it is limited by surface roughness below that temperature. The corner effect, in which the device corners have a lower threshold voltage than the top and sidewall Si/SiO/sub 2/ interfaces, shows up at temperatures lower than 150 K.

Dielectrophoretic self-assembly of polarized light emitting poly(9,9-dioctylfluorene) nanofibre arrays

Conjugated polymer based 1D nanostructures are attractive building blocks for future opto-electronic nanoscale devices and systems. However, a critical challenge remains the lack of manipulation methods that enable controlled and reliable positioning and orientation of organic nanostructures in a fast, reliable and scalable manner. To address this challenge, we explore dielectrophoretic assembly of discrete poly(9,9-dioctylfluorene) nanofibres and demonstrate site selective assembly and orientation of these fibres. Nanofibre arrays were assembled preferentially at receptor electrode edges, being aligned parallel to the applied electric field with a high order parameter fit (∼ 0.9) and exhibiting an emission dichroic ratio of ∼ 4.0. As such, the dielectrophoretic method represents a fast, reliable and scalable self-assembly approach for manipulation of 1D organic nanostructures. The ability to fabricate nanofibre arrays in this manner could be potentially important for exploration and development of future nanoscale opto-electronic devices and systems.

Analysis of charge transport in arrays of 28 kDa nanocrystal gold molecules

Arrays of 28 kDa nanocrystal gold molecules behave as weakly-coupled molecular solids comprising discrete nanoscale metallic islands separated by insulating ligand barriers. The key parameters which are found to dominate charge transport are (a) the single-electron nanocrystal charging energy, governed by the core diameter, the dielectric properties of the passivating ligands and classical electrostatic coupling between neighbouring cores; (b) the inter-nanocrystal tunnel barrier resistance that arises from the insulating nature of the ligand bilayers that separate the cores; and (c) the dimensionality of the network of current-carrying paths.

The High Frequency Electrical Properties of Interconnects on a Flexible Polyimide Substrate Including the Effects of Humidity

Flexible circuit board materials can be used to advantage in radio frequency and high-speed digital systems but an obstacle to their use is the lack of availability of information on the electrical properties of materials to high frequencies and, in particular, the variation in dielectric constant and loss tangent as a function of frequency. This makes accurate electromagnetic simulation of high frequency flexible interconnects difficult. The variation of the electrical properties of these materials as a function of environmental parameters, such as humidity, is also unknown at higher frequencies. This paper has, using microwave resonators, investigated the electrical properties from 2 GHz to 18 GHz of a polyimide flexible circuit board material saturated at 25% RH and at 85% RH relative humidity levels. Rigid circuit board materials FR4 and CER-10 were also measured as reference materials. The relative permittivity, εr, total loss, αT, and loss tangent, tan δ, have been extracted from the measurements for each material. The strong influence of conductor losses on overall losses when using thin materials such as flex at high frequency has also been evaluated and quantified in these measurements. In addition to the resonators used for measurement of material electrical properties, microstrip transmission lines were also included on each test sample and their s-parameters were measured at the same time and under the same conditions as the resonators. Comparisons between the measured electrical performance of the microstrip transmission lines and simulations of the lines based on the extracted material parameters show a high degree of correlation, indicating the validity of both the use of the resonator approach and overall loss measurement methodologies.

Capacitance and Conductance for an MOS System in Inversion, with Oxide Capacitance and Minority Carrier Lifetime Extractions

Experimental observations for the In_0.53Ga_0.47As metal-oxide-semiconductor (MOS) system in inversion indicate that the measured capacitance (C) and conductance (G or G_m), are uniquely related through two functions of the alternating current angular frequency (ω). The peak value of the first function (G/ω) is equal to the peak value of the second function (-dC/dlog_e(ω) ≡ -ωdC/dω). Moreover, these peak values occur at the same angular frequency (ω_m), that is, the transition frequency. The experimental observations are confirmed by physics-based simulations, and applying the equivalent circuit model for the MOS system in inversion, the functional relationship is also demonstrated mathematically and shown to be generally true for any MOS system in inversion. The functional relationship permits the discrimination between high interface state densities and genuine surface inversion. The two function peak values are found to be equal to C_ox²/(2(C_ox + C_D)) where C_ox is the oxide capacitance per unit area and C_D is the semiconductor depletion capacitance in inversion. The equal peak values of the functions, and their observed symmetry relation about ω_m on a logarithmic ω plot, opens a new route to experimentally determining C_ox. Finally, knowing ω_m permits the extraction of the minority carrier generation lifetime in the bulk of the In_0.53Ga_0.47As layer.

On the activation of implanted silicon ions in p-In0.53Ga0.47As

We present a systematic study of Si dopant implantation and activation in p-type In0.53Ga0.47As in an attempt to optimize the source and drain regions of an n-channel III-V metal?oxide?semiconductor field-effect transistor. Test structures based on the transfer length method were fabricated on Si-implanted p-In0.53Ga0.47As/p-InP buffer/semi-insulting InP. A Doehlert design of experiment (DOE) was used to investigate the effect of annealing temperature and time on the electrical properties of the samples. The DOE covered an experimental domain of 625?725??C and 15?45?s. The current?voltage characteristics of all tested structures exhibited excellent ohmic behavior. The DOE revealed a minimum sheet resistance of (195.6 ? 3.4) ?/? for an optimum anneal condition of 715??C for 32?s. Nonalloyed Au/Ge/Au/Ni/Au contacts, on the sample annealed at 675??C for 30?s (center point of the experimental domain), exhibited a low specific contact resistance of (7.4 ? 4.5)???10?7?? cm2. The sample annealed at 675??C for 30?s was further investigated using secondary ion mass spectrometry (SIMS) and cross-sectional transmission electron microscopy (XTEM) analyses. SIMS revealed that Si ions did not diffuse with annealing, while XTEM showed the formation of characteristic loop defects potentially responsible for the sheet resistance and specific contact resistance degradation.

A novel fast technique for detecting voiding damage in IC interconnects

A novel technique has been developed that is sensitive to the degree of voiding damage induced in a wide-line interconnect test structure. The technique is based on the measurement of the scattering parameters (S-parameters) of a simple metal-line test structure over a range of high frequencies. The transmission-line parameter, G (leakage conductance), which is calculated from the S-parameter measurements, is shown to be sensitive to distributed voiding, especially in wider lines. This is significant for the following reasons: (1) the measurement is fast, at a few seconds per test structure; (2) it can be performed at wafer level; (3) it does not rely on overstressing of the metallization; and (4) it is sensitive to the amount of voiding damage present in wide interconnect lines. Potential applications for this technique are: (a) an in-line statistical reliability control (SRC) test for the detection of stress voids induced during processing, and (b) an in-line SRC test for electromigration when preceded by a suitable current pre-stress step.

A novel approach to the estimation of confidence limits for BJT model sets using a bootstrap technique

In this paper, a novel method for the estimation of confidence intervals of extracted parameter values is proposed. The technique is based on a bootstrap method which evaluates the error distributions which are associated with parameter extraction techniques. Using this technique, a confidence interval can then be estimated for extracted parameter values. Results are presented for DC, capacitance and high frequency measurements.

DNA-Templated Assembly of Conducting Gold Nanowires

The use of DNA to template the assembly of gold nanowires from gold nanoparticles is reported. Double-stranded calf thymus DNA, was deposited on a polystyrene-coated silicon wafer substrate. The substrate was then exposed to an aqueous dispersion of positively charged gold nanoparticles (~ 4 nm diameter), which adsorbed at the negatively charged DNA template. The adsorbed nanoparticles were then enlarged and enjoined by electroless deposition leading to formation of continuous nanowires of 85 nm average diameter. Gold electrodes were then overlaid on individual nanowires using conventional lithographic techniques. Two-terminal current-voltage measurements were employed to characterize the electrical characteristics of single nanowires. The nanowires exhibit resistivity values -7 Ωm. These and related findings have implications for the design and assembly of next generation electronic devices.