nan Liangchun

High-Frequency Switching of SiC High-Voltage LJFET

In this paper, inductive-load switching of a high-voltage lateral JFET (HV-LJFET) on 4H-SiC is investigated with a monolithically integrated driver and with an external driver for high-frequency, high-temperature applications. A new ldquocapacitor-coupledrdquo gate driver circuitry is proposed and optimized to utilize a standard MOS driver and enable fast switching speed without the need for a negative power supply. Switching times and losses of the silicon carbide (SiC) HV-LJFET are characterized under various driver conditions and device temperatures. The results reveal that the temperature-independent, high switching speed of the SiC LJFET makes it possible to hard-switch at 3 MHz, 200 V, 1.2 A, and 250degC with good efficiency, significantly higher than silicon devices with similar voltage ratings.

Large random telegraph noise in sub-threshold operation of nano-scale nMOSFETs

We utilize low-frequency noise measurements to examine the sub-threshold voltage (sub-VTH) operation of highly scaled devices. We find that the sub-VTH low-frequency noise is dominated by random telegraph noise (RTN). The RTN is exacerbated both by channel dimension scaling and reducing the gate overdrive into the sub-VTH regime. These large RTN fluctuations greatly impact circuit variability and represent a troubling obstacle that must be solved if sub-VTH operation is to become a viable solution for low-power applications.

The Origins of Random Telegraph Noise in Highly Scaled SiON nMOSFETs

Random telegraph noise (RTN) has recently become an important issue in advanced circuit performance. It has also recently been used as a tool for gate dielectric defect profiling. In this work, we show that the widely accepted model thought to govern RTN behavior cannot be used to describe our experimental observations. The basis of this model (charge exchange between inversion layer and bulk oxide defects via tunneling) is inconsistent with our RTN observations on advanced SiON nMOSFETs with 1.4 nm physical gate oxide thickness. Alternatively, we show that RTN is qualitatively consistent with the capture and emission of inversion charge by interface states. Our results suggest that a large body of the low-frequency noise literature very likely needs to be re-interpreted.

Oxide Reliability of SiC MOS Devices

Silicon carbide possesses excellent material properties for high temperature, high frequency and high power applications. Among all the device structures, MOSFET has advantages such as low gate leakage current, easier device control etc., and therefore highly desirable. However, it has long been a common believe that the gate oxide breakdown reliability is a show-stopper, particularly at high temperature where SiC devices are expected to excel. In this paper, we report that the thermally grown gate oxide on 4H-SiC is intrinsically reliable even at temperature as high as 375degC. We further show that even with the current SiC processing technology, devices with 10 cm2 active area can still achieve 100-year lifetime @ E < 2.9 MV/cm and 375degC.

Modeling and Optimal Device Design for 4H-SiC Super-Junction Devices

In this paper, a new and easy-to-implement analytical model is developed for the breakdown voltage and on-resistance of 4H-SiC superjunction devices. By considering the 2-D charge compensation effects, electric field distribution along the critical path has been modeled, and the device breakdown voltage has been calculated. Charge imbalance effects have also been accounted for. Results from the model have been validated by extensive numerical simulation for a large variety of device dimensions and doping concentrations. The proposed model is simple yet accurate for a relatively complicated and challenging structure. Through a device design example with a given set of constraints, it has been demonstrated that the proposed model can quickly provide an optimum structure for what might take weeks through numerical simulation. It can therefore provide useful guidelines for future developments of superjunction devices on 4H-SiC.

New methods for the direct extraction of mobility and series resistance from a single ultra-scaled device

In summary, we have presented a novel wafer-level Hall mobility (μH) measurement methodology which can be implemented in any conventional wafer prober (no specialized equipment needed). In addition, we demonstrated a simple RSD extraction scheme with verifiable accuracy. Both techniques work directly on a single ultra-scaled MOSFET, providing an elegant solution to two very difficult but important measurements. The authors acknowledge the Office of Microelectronic Programs at NIST for financial support.

A new interface defect spectroscopy method

A new interface defect spectroscopy method based on variable height charge pumping capable of observing the amphoteric nature of Si/SiO2 interface states in production quality sub-micron devices is demonstrated. It can help to resolve the long standing debate about the true nature of Si/SiO2 interface states. Additionally, we show that this is a powerful technique for studying other important material systems.

Design of high temperature SiC LJFET-based logic inverter and integrated gate driver

I Power integrated circuit based on SiC lateral JFET promises to operate at temperatures beyond 300°C. In this paper, design constraints in selecting the LJFET threshold voltage, the load resistance and the DC power supply voltage to obtain proper gate driver circuit functionality in the temperature range of 25°C∼300°C are investigated through extensive experimentation. The study shows that an appropriate load resistance needs to be chosen for a given LJFET for the trade-off between good output voltage swing and a good output current driving capability. It is also shown that increasing the power supply voltage usually increases both the voltage swing and output current capability, with the cost of increased power consumption. Measurements at various temperatures up to 300°C reveal that the output voltage swing decreases significantly at higher temperatures. The design window for LJFET threshold voltage is found to be 0V∼2.0V at 25°C but narrows down to 0.5V∼1.2V at 300°C. Such a threshold voltage window is considered to be achievable in a large scale IC facility. Finally, a 4-stage gate driver circuit capable of operation at both 25°C and 300°C is reported. This work aims at providing a foundation for the fabrication process and device design of a possible full-scale power IC on SiC.

A fast, simple wafer-level Hall-mobility measurement technique

Mobility is a good indicator of device reliability. High channel mobility is one of the biggest challenges especially in novel devices such as high-k based MOSFET, III–V devices and SiC power MOSFET etc. Accurate measurement of channel mobility is required for studying the limiting mechanism of mobility. Hall mobility is more favorable than effective mobility or field effect mobility because it takes into account only the mobile charges, which is essential for measuring novel devices that have a very high trap density. However, regular Hall measurement involves a bulky system and tedious sample preparation, which inhibit frequent use. In this paper, we demonstrate a fast and easy to implement wafer-level Hall-mobility measurement technique that allows for large survey of many devices under various conditions.

An improved fast I d -V g measurement technology with expanded application range

Fast Id-Vg measurements on very high performance devices (very low channel ON-resistance) and larger area devices (therefore large gate capacitance) are subject to serious distortions. Methods to minimize these distortions are introduced in this paper; thus expanding the applicable range of this important measurement technique.