Liangliang Zhang

Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation

In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency gm/Id, intrinsic gain gm/gd, cutoff frequency ft , and maximum oscillation frequency fmax. The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process variation is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given

Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs

Low-frequency noise (LFN) in n-type silicon nanowire MOSFETs (SNWTs) is investigated in this letter. The drain-current spectral density exhibits significant dispersion of up to five orders of magnitude due to the ultrasmall dimensions of SNWTs. The measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed. At high drain current, however, the input-referred noise spectral density increases rapidly with the drain current, which indicates the significant impact of the ultranarrow source/drain extension regions of SNWTs. As a result, design optimizations to reduce the impact of parasitic resistance in SNWTs are necessary for analog/RF applications.

Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shurs model. The physical understanding of the apparent mobility in SNWTs is also discussed using fluxs scattering matrix method.

Challenges of 22 nm and beyond CMOS technology

It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

Selective Passivation of GeO2/Ge Interface Defects in Atomic Layer Deposited High-k MOS Structures

Effective passivation of interface defects in high-k metal oxide/Ge gate stacks is a longstanding goal of research on germanium metal-oxide-semiconductor devices. In this paper, we use photoelectron spectroscopy to probe the formation of a GeO2 interface layer between an atomic layer deposited Al2O3 gate dielectric and a Ge(100) substrate during forming gas anneal (FGA). Capacitance- and conductance-voltage data were used to extract the interface trap density energy distribution. These results show selective passivation of interface traps with energies in the top half of the Ge band gap under annealing conditions that produce GeO2 interface layer growth. First-principles modeling of Ge/GeO2 and Ge/GeO/GeO2 structures and calculations of the resulting partial density of states (PDOS) are in good agreement with the experiment results.

Random telegraph signal noise in gate-all-around silicon nanowire transistors featuring Coulomb-blockade characteristics

Random telegraph signal (RTS) noise is experimentally investigated in silicon nanowire transistors (SNWTs) fabricated with complementary-metal-oxide-semiconductor compatible top-down approach. The observed RTS is found to have Coulomb-blockade characteristics rather than those described by conventional Shockley–Read–Hall theory. The capture and emission time constants of oxide traps strongly depend on the gate bias due to strong quantum confinement and enhanced electrical field in nanowire structures. Amplitude of single RTS in SNWTs is found within 10%, while large amplitude of multilevel RTS up to 34% at room temperature is observed due to the ultranarrow channel and the behavior of independent multitraps in SNWTs. Widely spread time constants of oxide traps and slow RTS of very long-time constants (several hundred seconds) are also observed in SNWTs.

Characterization and analysis of gate-all-around Si nanowire transistors for extreme scaling

The gate-all-around (GAA) silicon nanowire transistor (SNWT) is considered as one of the best candidates for ultimately scaled CMOS devices at the end of the technology roadmap. This paper reviews our recent work on the characterization and analysis of this unique one-dimensional nanowire-channel device with three-dimensional surrounding-gate from experiments and simulation, including carrier transport behavior, parasitic effects, noise characteristics, self-heating effect, variability and reliability, which can provide useful information for the GAA device hierarchical modeling and device/circuit co-design.

EOT Scaling of

TiO₂/Al₂O₃/Ge gate stacks have promising characteristics for future germanium-channel high-performance MOSFETs. In this letter, TiO₂/Al₂O₃ bilayer high-k dielectrics with EOT 0.65 nm are demonstrated and used in Ge pMOSFETs for the first time, giving low subthreshold swing (71 mV/dec) and large on-state current (28 A/um). In addition, detailed investigations of these devices with two different gate metals - Al/W and Al/Pt - are performed for stable metal/TiO₂ interfaces and EOT scaling.

{\rm TiO}_{2}/{\rm Al}_{2}{\rm O}_{3}

The effect of Al2O3 atomic layer deposition (ALD) temperature on the border trap density (Nbt) of Al2O3/InGaAs gate stacks is investigated quantitatively, and we demonstrate that lowering the trimethylaluminum (TMA)/water vapor ALD temperature from 270 °C to 120 °C significantly reduces Nbt. The reduction of Nbt coincides with increased hydrogen incorporation in low temperature ALD-grown Al2O3 films during post-gate metal forming gas annealing. It is also found that large-dose (∼6000 L) exposure of the In0.53Ga0.47As (100) surface to TMA immediately after thermal desorption of a protective As2 capping layer is an important step to guarantee the uniformity and reproducibility of high quality Al2O3/InGaAs samples made at low ALD temperatures.

on Germanium pMOSFETs and Impact of Gate Metal Selection

Impacts of electron trapping/detrapping on the negative bias temperature instability (NBTI) characteristics in silicon nanowire transistors (SNWTs) with metal gates are experimentally studied in this paper. It is demonstrated that large amounts of as-grown defects, including both electron traps and hole traps, are induced by nanowire structure due to multiple surface crystal orientations of the cylinder nanowires. Quite different from conventional planar devices, both stress and recovery of NBTI in SNWTs are evidently impacted by electron trapping/detrapping behavior, due to the enhanced electrical field with cylinder surrounded gate, increased electron traps in the gate dielectrics and electron injection from metal gates. The generation of new-born trap-precursors in the gate dielectrics of SNWTs was also observed and the generation kinetics is discussed. These new-born precursors can be converted into traps after experiencing a grounded recovery phase and a pulse state, leading to additional unexpected reliability degradation of SNWTs.