Jing Zhuge

Analog/RF Performance of Si Nanowire MOSFETs and the Impact of Process Variation

In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency gm/Id, intrinsic gain gm/gd, cutoff frequency ft , and maximum oscillation frequency fmax. The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process variation is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given

Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs

Low-frequency noise (LFN) in n-type silicon nanowire MOSFETs (SNWTs) is investigated in this letter. The drain-current spectral density exhibits significant dispersion of up to five orders of magnitude due to the ultrasmall dimensions of SNWTs. The measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed. At high drain current, however, the input-referred noise spectral density increases rapidly with the drain current, which indicates the significant impact of the ultranarrow source/drain extension regions of SNWTs. As a result, design optimizations to reduce the impact of parasitic resistance in SNWTs are necessary for analog/RF applications.

Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shurs model. The physical understanding of the apparent mobility in SNWTs is also discussed using fluxs scattering matrix method.

Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that the tunneling current has a negligible contribution in charging and discharging the gate capacitance of TFETs. In spite of a higher resistance region in the short-gate TFET, the gate (dis)charging speed still meets low-voltage application requirements. A circuit analysis is performed on short-gate TFETs with different materials, such as Si, Ge and heterostructures in terms of voltage overshoot, delay, static power, energy consumption and energy delay product (EDP). These results are compared to MOSFET and full-gate TFET performance. It is concluded that short-gate heterostructure TFETs (Ge–source for nTFET, In0.6Ga0.4As–source for pTFET) are promising candidates to extend the supply voltage to lower than 0.5 V because they combine the advantage of a low Miller capacitance, due to the short-gate structures, and strong drive current in TFETs, due to the narrow bandgap material in the source. At a supply voltage of 0.4 V and for an EOT and channel length of 0.6 nm and 40 nm, respectively, a three-stage inverter chain based on short-gate heterostructure TFETs saves 40% energy consumption per cycle at the same delay and shows 60%–75% improvement of EDP at the same static power, compared to its full-gate counterpart. When compared to the MOSFET, better EDP can be achieved in the heterostructure TFET especially at low static power consumption.

New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency noise

A new method to fabricate self-aligned silicon nanowire transistors (SNWTs) has been realized on bulk silicon substrate by fully epi-free compatible CMOS technology. The SNWTs exhibit excellent immunity of short-channel effects (SCEs) and achieve high Ion/Ioff ratio of 2.6times108. The transportation characteristics, ballistic efficiency and low frequency noise of SNWTs are investigated for the first time.

Investigation on Variability in Metal-Gate Si Nanowire MOSFETs: Analysis of Variation Sources and Experimental Characterization

The characteristic variability in gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistors (SNWTs) is analyzed and experimentally investigated in this paper. First, the main variation sources in SNWTs are overviewed, with the detailed discussion on the specific sources of NW cross-sectional shape variation, random dopant fluctuation in NW source/drain extension regions and NW line-edge roughness (LER). Then, following the measurement-modeling approach, via calibrated statistical simulation that is based on the modified analytical model for GAA SNWTs with corrections of quantum effects and quasi-ballistic transport, the variability sources in SNWTs are experimentally extracted from the measured devices with 10-nm-diameter NW channels and TiN metal gate. The results indicate that NW radius variation and metal-gate work function variation dominate both the threshold voltage and on-current variations due to the ultrascaled dimensions and strong quantum effects of GAA NW structure. The NW LER also contributes, but relatively less, to the threshold voltage variation.

Investigation of Parasitic Effects and Design Optimization in Silicon Nanowire MOSFETs for RF Applications

The design of silicon nanowire MOSFETs (SNWTs) for RF applications is discussed in this paper based on 3-D simulation, including the impacts of the parasitic capacitances and resistance. The results indicate that large parasitic capacitances are a dominant factor for nanowire structure, which can significantly degrade the ac characteristics of SNWTs. Resistance of the ultranarrow source/drain extension (SDE) regions, which is the main contributor to the total series resistance of SNWTs, is another important factor influencing the device performance. The requirement of contact resistance of source/drain regions in SNWTs is relatively relaxed compared to the SDE regions. Considering the tradeoff between parasitic capacitances and resistance, optimization of the doping profile in SDE regions of SNWTs with 10-nm gate length is further investigated for RF applications.

High-Performance BOI FinFETs Based on Bulk-Silicon Substrate

A new body-on-insulator (BOI) FinFET device structure based on bulk-Si substrate has been proposed and experimentally demonstrated in this paper. In comparison with other bulk FinFETs, the BOI FinFET features the localized insulator below the Si-Fin body, which can achieve both low source/drain (S/D) parasitic resistance and effective suppression of the S/D leakage beneath the Si-Fin channel, as well as good heat dissipation capability. The device fabrication process is basically compatible with conventional CMOS technology. High drive current, low subthreshold swing, and excellent short-channel behavior are observed in the fabricated BOI FinFETs.

Investigation of Nanowire Line-Edge Roughness in Gate-All-Around Silicon Nanowire MOSFETs

In this paper, the effects of nanowire line-edge roughness (LER) in gate-all-around silicon nanowire MOSFETs (SNWTs) are comprehensively investigated through 3-D statistical simulation. The LER impacts on both the device performance variation and mean value degradation are discussed in detail. Due to the unique nature of a nanowire structure, the LER in SNWTs contains two degrees of freedom, which allows the nanowire edges to vary in arbitrary transverse direction and which is different from the LER in traditional devices with one degree of freedom. In order to identify the relative importance of the diameter and center position variations, the nanowire LER can be considered as the combination of two basic types: One has a varied diameter with a fixed center (type A), and the other has a varied center position with a fixed diameter (type B). The results indicate the tradeoff between these two types of LER, with type A of a larger performance variation and type B of a larger performance degradation. Furthermore, as the gate length Lg shrinks below the correlation length Λ of the nanowire LER, the impacts from the source/drain extension region will dominate the variation. The impact of the main LER parameters is discussed for the scaled case with a non-Gaussian distribution in the device electrical parameters observed, and a new statistical method is proposed for better evaluation. On the other hand, the performance variation becomes insensitive to the correlation length in the case of Λ > Lg, which indicates a higher tolerance for the nanowire LER design in ultrascaled SNWTs. The optimized LER parameters are also given for the nanowire LER design with acceptable performance variation and suppressed mean value degradation in SNWTs.

Random telegraph signal noise in gate-all-around silicon nanowire transistors featuring Coulomb-blockade characteristics

Random telegraph signal (RTS) noise is experimentally investigated in silicon nanowire transistors (SNWTs) fabricated with complementary-metal-oxide-semiconductor compatible top-down approach. The observed RTS is found to have Coulomb-blockade characteristics rather than those described by conventional Shockley–Read–Hall theory. The capture and emission time constants of oxide traps strongly depend on the gate bias due to strong quantum confinement and enhanced electrical field in nanowire structures. Amplitude of single RTS in SNWTs is found within 10%, while large amplitude of multilevel RTS up to 34% at room temperature is observed due to the ultranarrow channel and the behavior of independent multitraps in SNWTs. Widely spread time constants of oxide traps and slow RTS of very long-time constants (several hundred seconds) are also observed in SNWTs.