Libin Yao

A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS

A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.

A 0.8-V, 8-/spl mu/W, CMOS OTA with 50-dB gain and 1.2-MHz GBW in 18-pF load

A low-power low-voltage OTA with rail-to-rail output is introduced. The proposed topology is based on the common current mirror OTA topology and provide gain enhancement without extra power consumption. Implemented in a standard 0.25/spl mu/m CMOS technology, the proposed OTA achieves 50 dB DC gain in 0.8 V supply voltage. The GBW is 1.2MHz and the static power consumption is 8/spl mu/W while driving 18pF load. The class AB operation increases the slew rate and still maintains low static biasing current. This topology is suitable for low-power low-voltage switched-capacitor application.

Fast-settling CMOS two-stage operational transconductance amplifiers and their systematic design

Compared to single-stage OTAs, two-stage OTAs have higher gain and output swing, but more poles and zeros and thus have more complex settling behavior. Two structures of two-stage OTAs that have good settling performance are introduced. By analyzing the settling behavior of the third order system, a set of poles and zeros parameters are extracted. A design procedure for minimum settling time of these two OTAs is described. Finally two design examples for minimum settling time are presented. These high-speed OTAs are suitable for high-speed switched-capacitor applications.

A 1-V, 1-MS/s, 88-dB sigma-delta modulator in 0.13-/spl mu/m digital CMOS technology

A low-voltage switched-capacitor fourth-order /spl Sigma/-/spl Delta/ modulator using full feed-forward is introduced. It has two advantages: the unity signal transfer function and reduced signal swings inside the /spl Sigma/-/spl Delta/ loop. These features greatly relax the DC gain and output swing requirements for OTAs in the deep submicron CMOS /spl Sigma/-/spl Delta/ modulator. With careful signal scaling, signal swings inside the loop can be suppressed to less than 50% of the reference voltage, which is highly desirable by low-voltage designs. Implemented by a 0.13-/spl mu/m pure digital CMOS technology, the /spl Sigma/-/spl Delta/ modulator achieves 1-MS/s conversion speed and 88-dB DR with 7.4-mW power dissipation under 1.0-V power supply voltage.

A 1 V 88 dB 20 kHz /spl Sigma//spl Delta/ modulator in 90 nm CMOS

A third-order single-loop SC /spl Sigma//spl Delta/ modulator is realized in a standard 90 nm digital CMOS technology. The modulator achieves 88 dB dynamic range for a 20 kHz signal bandwidth with an OSR of 100. Power consumption is 140 /spl mu/W from a 1 V supply, and the chip core size is 0.18 mm/sup 2/.

Mismatch characterisation of chip interconnect resistance

Many analog circuits use matched resistors on chip. The resistors have two components: the resistive elements and the interconnects. The resistive elements have good matching properties. However, the resistance of the interconnects - especially of the contacts and vias - is only guaranteed to be within certain wide limits. If the matched resistors are low-ohmic, then the interconnect dominates the mismatch equations. This is often solved by oversizing the interconnect or by avoiding structures with lots of interconnect. We prefer to characterize these interconnects or even to build resistors using only interconnects. The measurement results show that the interconnect resistance can match as well as poly resistors in the same 0.18 /spl mu/m technology.

LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS: 90 nm AN ADVANTAGE?

Moving into ultra-deep-submicron CMOS technologies, the design of Σ-Δ ADCs faces more challenges. Among them important ones are the restriction from the decreased supply voltage, the higher distortion and degraded device characteristics. The reduced supply voltage decreases the signal swing and lower noise floor is required to maintain the same signal-to-noise ratio. On the other hand, some advantages are gained. Important ones are the reduced threshold voltage of the transistor and lower power consumption of the digital circuits. In this paper, low-power low-voltage Σ-Δ ADC design strategies are introduced and design techniques in ultra-deep-submicron CMOS technologies are presented. As an example, a 1 V, 20 kHz, 88 dB, 140 µW Σ-Δ modulator design in a 90 nm CMOS technology is presented.