W. Sansen

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

AMGIE-A synthesis environment for CMOS analog integrated circuits

A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization. It follows a hierarchical refinement strategy for more complex cells and is process independent. The sizing is based on an improved equation-based optimization approach, where the circuit behavior is characterized by declarative models that are then converted in a sequential design plan. Supporting tools have been developed to reduce the total effort to set up a new circuit topology in the systems database. The performance-driven layout generation tool guarantees layouts that satisfy all performance constraints. Redesign support is included in the design flow management to perform backtracking in case of design problems. The experimental results illustrate the productiveness and efficiency of the environment for the synthesis and process tuning of frequently used analog cells.

A CMOS large-swing low-distortion three-stage class AB power amplifier

A CMOS power amplifier with a class AB rail-to-rail output stage is presented. By using a three-stage amplifier with double Miller compensation, the harmonic distortion of the output stage is suppressed by the internal feedback loops. This approach is thoroughly investigated, and it is shown that a three-stage amplifier has apparent advantages for DC gain, harmonic distortion, and power-supply rejection ratio (PSRR). A realized prototype for ISDN applications with a gain bandwidth (GBW) of 5 MHz and with -80-dB THD at 10 kHz for an output current of 20 mA in a load of 81 Omega is presented. >

An accurate statistical yield model for CMOS current-steering D/A converters

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.

A layout-aware synthesis methodology for RF circuits

In this paper a layout-aware RF synthesis methodology is presented. The methodology combines the power of a differential evolution algorithm with cost function response modeling and integrated layout generation to synthesize RF Circuits efficiently, taking into account all layout parasitics during the circuit optimization. The proposed approach has successfully been applied to the design of a high-performance downconverter mixer circuit, proving the effectiveness of the implemented design methodology.

Electrothermal simulation and design of integrated circuits

An accurate prediction of the electrothermal behavior of power integrated devices is required to design circuits in an efficient way. An electrothermal simulator (ETS) is a combination of SPICE with finite element code, in a relaxation procedure. It simulates the full electrothermal behavior of integrated circuits. Static and dynamic simulations of typical examples, reveal the value of ETS for high-power applications. Some specific design rules are derived. They are simple formulas, which estimate the temperature (gradients) on chip. They can be used before any CPU-time consuming simulation takes place which allows a more efficient design and prototype phase. >

A CMOS multi-parameter biochemical microsensor with temperature control and signal interfacing

A fully-integrated microsensor chip allows continuous monitoring of concentrations of blood gases (pH, pO/sub 2/, pCO/sub 2/), ions, and biomolecules, and a conductometric measurement. The chip monitors 7 different chemical properties and includes temperature control and an EPROM. It occupies 25.7 mm/sup 2/ in a standard 1.2 /spl mu/m CMOS process including chemical sensor postprocessing and operates at 5 V.

CYCLONE: automated design and layout of RF LC-oscillators

This paper presents a specification-driven layout-aware CMOS RF LC-oscillator design tool called CYCLONE. Circuit sizing and layout generation are integrated in the overall oscillator optimization. The tool optimizes the device sizes and also determines the optimal geometrical parameters of the on-chip inductor and automatically performs electromagnetic simulations to exactly calculate its losses during sizing. For the other devices in the oscillator circuit, being gain cell and varactor diode, it uses a technology-independent template-based layout generation approach to obtain accurate predictions of the actual layout parasitics. The device sizing of the gain cell is based on an operating-point linearized BSIM3 model of the gain cell transistors. The varactor diode is sized based on the BSIM3 source/drain diode models of the pMOS transistor. All parasitics; are incorporated in a global optimization of the complete oscillator circuit. After optimization of the circuit, the layout can be exported to a standard GDSII format for processing. The capabilities of the tool are demonstrated by several design experiments.

A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC

This brief analyzes the systematic errors that limit the intrinsic accuracy of a digital-to-analog converter (DAC). A new switching scheme is proposed that exhibits special properties: it cancels the linear and quadratic gradient errors at the MSB level. We explain why this scheme has those properties and how to construct it. This scheme excels at reducing edge-effects occurring at the side of the array. No extracted information from the error profile is required. This increases the robustness of the scheme and reduces the need for reprocessing. The effectiveness of this scheme is demonstrated by applying it to the measured error profile of a 14-b current-steering converter without dummies. This shows that 14-b current-steering converters can be constructed without any dummy rows or columns at all.