M. Steyaert

A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC

In this paper, a 14-bit, 150-MSamples/s current steering digital-to-analog converter (DAC) is presented. It uses the novel Q/sup 2/ random walk switching scheme to obtain full 14-bit accuracy without trimming or tuning. The measured integral and differential nonlinearity performances are 0.3 and 0.2 LSB, respectively; the spurious-free dynamic range is 84 dB at 500 kHz and 61 dB at 5 MHz. Running from a single 2.7-V power supply, it has a power consumption of 70 mW for an input signal of 500 kHz and 300 mW for an input signal of 15 MHz. The DAC has been integrated in a standard digital single-poly, triple-metal 0.5-/spl mu/m CMOS process. The die area is 13.1 mm/sup 2/.

A 2 V CMOS cellular transceiver front-end

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-/spl mu/m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-/spl mu/m CMOS technology, without tuning or trimming.

A CMOS monolithic /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer for DCS-1800

A monolithic 1.8-GHz /spl Delta//spl Sigma/-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-/spl mu/m CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2/spl times/2 mm/sup 2/. To investigate the influence of the /spl Delta//spl Sigma/ modulator on the synthesizers spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in /spl Delta//spl Sigma/ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints.

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization

A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f/sup 3/ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f/sup 3/ phase-noise corner is minimized to be less than 15 kHz. The VCOs are implemented in a three-metal layer, 0.65-/spl mu/m BiCMOS process, using only MOS active devices.

A single-chip CMOS transceiver for DCS-1800 wireless communications

This CMOS transceiver chip for the DCS-1800 wireless communication system is realized in a 0.25 /spl mu/m CMOS process. The realization of a CMOS transceiver that complies with the specifications of a high-quality digital-wireless system requires overall integration of architecture, building block and transistor-level design. A highly-integrated architecture minimizes the number of high-frequency external nodes, as these are difficult to drive with CMOS circuits. Up- and downconversion topologies allow at the same time mixing and a high-quality on-chip single-ended to differential conversion. Extra buffers between building blocks optimize overall circuit performance.

A CMOS 18 THz/spl Omega/ 248 Mb/s transimpedance amplifier and 155 Mb/s LED-driver for low cost optical fiber links

The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 /spl mu/m digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is 60 mA which allows a 155 Mb/s optical data-rate. The receiver is a three-stage transimpedance amplifier followed by a signal converter which provides digital output signal levels. The three-stage configuration makes possible the realization of a high transimpedance (150 k/spl Omega/), necessary to obtain a high sensitivity, combined with a high bandwidth. The achieved optical data-rate is 240 Mb/s for 1 /spl mu/A input modulation currents. This results in a transimpedance bandwidth of 18 THz/spl Omega/, which is one order of magnitude higher than recently published circuits. The speed performance of the total link is limited by the optical time-constant of the LED, leading to a 155 Mb/s optical link, designed for use in four-fiber interboard connections in 622 Mb/s B-ISDN systems. >

A Fully Integrated

In this work we present a fully integrated first order continuous-time ΔΣ ADC made in a pentacene-based dual-gate organic thin-film transistor technology on flexible plastic foil. The ADC achieves a precision of 26.5 dB at a clock speed of 500 Hz and draws 100 μA from a 15 V power supply. As sub-blocks of the ADC, we also present a Vt -insensitive single-stage differential amplifier with 10 kHz GBW, a 3-stage operational amplifier, an integrator, a comparator and a level shifter. The circuits are designed following a strict Vt -insensitive design strategy and use high-pass filters for offset cancellation. The active area is 13 × 20 mm2.

\Delta \Sigma

To obtain a high resolution CMOS current-steering digital-to-analog converter, the matching behavior of the current source transistors is one of the key issues in the design. At this moment, these matching properties are taken into account by the use of time consuming and CPU intensive Monte Carlo simulations. In this paper a formula is derived that allows us to accurately describe the impact of the mismatch on the INL (integral non-linearity) yield of current-steering D/A converters without any loss of design time.

ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil

Research over the last ten years has resulted in attempts toward single-chip CMOS RF circuits for Bluetooth, global positioning system, digital enhanced cordless telecommunications and cellular applications. An overview of the use of CMOS for low-cost integration of a high-end cellular RF transceiver front-end is presented. Some fundamental pitfalls and limitations of RF CMOS are discussed. To circumvent these obstacles, the choice of transceiver architecture, circuit topology design, and systematic optimization of the different transceiver blocks is necessary. Moreover, optimization of the transceiver as one single block by minimizing the number of power-hungry interface circuits is emphasized. As examples, a fully integrated cellular transceiver front-end, a low-power extremely low noise-figure low-noise amplifier, and a very efficient power amplifier are demonstrated.

An accurate statistical yield model for CMOS current-steering D/A converters

A 1.8 GHz fully integrated Voltage Controlled Oscillator (VCO) is presented. Through inductor optimization, the phase noise is as low as -127.5 dBc/Hz at 600 kHz and -142.5 dBc/Hz at 3 MHz. A 28% wide tuning range is achieved with a 1.8 V power supply. The VCO exceeds the DCS-1800 phase noise requirements with at least 4 dB over the whole DCS-1800 frequency band. The VCO is implemented in a 2-metal layer, 0.25 /spl mu/m standard CMOS technology, using no external components nor additional processing steps.