Lim Teck Guan

Bi-directional optical communication at 10 Gb/s on FR4 PCB using reflow solderable SMT transceiver

We report the development of 10 Gbps bi-directional optical data communications on FR4 PCB to realize opto-electronic circuit board (OECB). The work includes the design, fabrication and high-speed performance of a 10 Gbps surface mount optical transceiver module that can be reflow soldered, developing efficient optical coupling methods using precise injection molded lenses and studying their attachment methods to the optical source and receiver, realizing efficient optical coupling between transmitter and receiver subsystems for a multi mode epoxy waveguide on the PCB and developing a test vehicle. The compact and highly integrated SMT optical transceiver module in multilayer LTCC substrate consists of optical devices like VCSEL and PIN photo diode and the electrical circuits like VCSEL driver, trans impedance amplifier (TiA) and limiting amplifier (LA). The module contains a cavity, in which the electrical, optical devices and passives are mounted using passive attachment methods, a recess to house a lens and locator holes to align the lens with the VCSEL and PIN. The lens is an injection molded epoxy lens with biconvex elements for both transmitter and receiver integrated as a single element to improve the coupling between the source and the waveguide on the PCB. The module is designed to relax the assembly tolerances of optical elements so that normal conventional electronic assembly process can be used. Solder bumps are formed on the bottom layer of the LTCC to convert the module into a cavity down SMT package. The waveguides are made of high temperature epoxy material and are attached to the PCB using adhesive material. The 45deg mirrors are formed through laser ablation process. The module is reflow soldered using conventional reflow oven. The opto-electronic circuit board (OECB) is performance evaluated and performance results are presented.

Fabrication and Optimization of the 45° Micro-mirrors for 3-D Optical Interconnections

This report experimentally demonstrated the fabrication and optimization of 45° micro-mirror forming process in the polymer waveguide layer for optical interconections. The fluorinated acrylate waveguide is consisted of stacking of the lower cladding, core and upper cladding layer. The guide core (70 um × 70 um) is fabricated by the soft molding method and the cladding layers are fabricated by spin-coating. The mirrors are fabricated by mechanical dicing using a 90° diamond dicing blade. The characteristics of the mirror, i.e., angle, surface quality and reflectivity are critical in achieving an efficient optical coupling of the active devices and the waveguide to form a 3-D optical interconnection. Scanning electron microscopy (SEM) and white light interferometer were used for the characterization of micro-mirror. The quality of the micro-mirror, which affecting the optical coupling in the polymer waveguide is of crucial for the success of the optical interconnections. The roughness and angle of mirror is important criteria in achieving an efficient optical coupling. Mirror surface roughness, measured by white-light interferometer, is of 316 nm with standard deviation of 0.006. The angle of the mirror which was measured by SEM and the white-light interferometer, met the requirement of 45 ± 1°. Larger angle tolerance will diversify the laser beam, lose its verticality and off targeting the photo-detector. In order to meet the performance specification, tighter process control and optimization of the dicing parameters are required to minimize the optical transmission loss. Detailed of each process are discussed in this paper.

Optimization and Characterization of Flexible Polymeric Optical Waveguide Fabrication Process for Fully Embedded Board-level Optical Interconnects

Optical interconnections on printed circuit board are promising approach for use throughout the backplane and motherboard. Optical interconnect with its low propagation loss and high data-transfer density become the key driver to solve the limitation of electrical interconnections which fail to meet with increasing data rate requirement The advantages of embedded polymer waveguide as optical interconnects is the potential compatibility with current PCB or silicon manufacturing process which could facilitate a smooth technology transition from electrical to optical technologies. This paper reports on optimization of the fabrication process of 10 cm long flexible polymer waveguide layer with 45° micro-mirror on a PI film by using soft molding to achieve fully embedded board-level optoelectronic interconnects. The photo-active UV-curable fluorinated acrylate resin with low propagation loss (0.05 dB/cm @ 830 nm), WIR30-RI series (Chemoptics) was chosen as clad and core (70 ¿m × 70 ¿m) materials, respectively. The waveguide layers are sandwiched between two polyimide films which support and protect the waveguide layer. Soft molding process is developed to replicate the polymer waveguide. It is known that oxygen inhibition is the key issue when UV-curing the acrylate coating under oxygen atmosphere. Nitrogen shielding is successfully eliminating the oxygen inhibition effect and has improved the surface condition. Scanning electron microscope (SEM) was used to analyze the effectiveness of the optimization process. The 45 micro-mirror in waveguide was formed by using 90° V-shaped diamond blade. The propagation loss of fabricated waveguide is -0.3 dB/cm at 850 nm wavelength. Detailed of each process are discussed in the paper.

A novel compact antenna with a low profile demonstrated on embedded wafer level packaging (EMWLP) technology

In an RF front-end module, the reduction of the antenna size is a challenge since it is dependent on the frequency of operation. In this paper, a method of antenna miniaturization is introduced, by employing a novel meander CPWG feed structure as well as reducing the footprints of both radiating structure and the feed structure. In one of the proposed structures, the bandwidth can be enhanced by introducing a slotted ground plane for better matching. The structures are fabricated on cost-effective platforms using embedded wafer level packaging (EMWLP) and FR-4 laminates, with a compact footprint and low profile achieved.

Study of high speed interconnects of multiple dies stack structure with Through-Silicon-Via (TSV)

Die stacking is widely adopted for high chip count systems to reduce the requirement of substrate area. The incorporation of Through-Silicon-Via (TSV) as vertical interconnects further reduces the interconnect path length from the top die to substrate. As the fabrication resolution keeps on shrinking, devices of even higher chip count are required to be assembled in a single package, which results in even longer 3D interconnects. As such, accurate modelling of high speed interconnects is essential for the high frequency systems. In this work, 3D modelling and Full wave EM simulation were performed on the interconnect path which consists of TSV, metal re-distribution Layer (RDL) and bumps. Effect of the different number of die stack was analyzed based on the simulation results.

High frequency characterization of through silicon via structure

In 3D package, through silicon via (TSV) have been used to achieve smaller size, better performance stacked package. However to effectively utilize TSV for high frequency package design, the high frequency performance of TSV structure has to be precisely characterized. In this work, a method that allows the high frequency extraction of TSVs S-parameter is presented. Extraction is basically done by using a number of line test structures and back-to-back via-line-via structures. This method of extraction does away with the need to perform probing both on top and below the wafer and thus do not require the use of high cost and complex probe station setup.

FOWLP electrical performances

Fan Out-Wafer Level Packaging (FO-WLP) has been recognized as the main electronic packaging and integration technology. It is cost effective and has good electrical performance as compared to the Silicon Interposer. Currently, there are many different versions of this FO-WLP technology being developed with the objective to increase the routing density. In order to design integrated circuit or package the electrical chip using the FO-WLP, it is essential to characterize electrical parameters. In this paper, the Redistribution Layers (RDL) first version of the FO-WLP electrical parameters and their test structures are provided.

Substrate opening to increase solder joint reliability and circuit integration

A novel solution to reduce the effect of coefficient of thermal expansion (CTE) mismatch between the package and the circuit board is proposed here. In this solution, the circuit board area directly beneath the package is removed to form a patterned opening. It is believed that the opening provide an additional direction for the circuit board expansion. The simulated result showed that the solder reliability of the substrate opening is better than using underfill. Depending on the requirement, the design of the opening such as the shape and dimension can be optimized. For higher circuit integration density, other package or module can be integrated through the opening. The proposed solution is simple as it only requires to form through opening in the circuit board. It does not require the costly underfill process.

Integrated Optical Carrier for Optical/Electrical Interconnect

A simple and novel design, integrating discrete commercial micro-lens and vertical illuminated optoelectronic component in a substrate with high accuracy, is presented here. Without affecting the optical performances, this integrated optical carrier also allows high-frequency radio-frequency interconnects. This feature is critical for high-speed operation. The high accuracy integrated optical carrier improves the optical coupling efficiency and helps to relax the tight circuit assembly tolerance requirement. The integrated optical carrier can be used for various photonic applications which employ vertical illuminated optoelectronic components. An integrated optical carrier prototype is designed here for the optical electrical interconnect printed circuit board (OECB). For this OECB design, the simulated results show that the integrated optical carrier helps to give an assembly misalignment tolerance of more than ±20 μm with an increase of 1 dB coupling loss. In addition, the simulated optical insertion loss from the transmitter to the receiver is less than 1.4 dB. The optical performance of the prototype integrated optical carrier is measured and compared with the simulation results to ascertain the design concept. For different OECB waveguide designs, dimensions and positions, this integrated optical carrier design is amended to give a better performance and misalignment tolerance.