David Soon Wee Ho

Through Silicon Via interposer for millimetre wave applications

A novel Through Silicon Via (TSV) structure to mitigate the high electrical loss at high frequency is presented here. At low frequency, the loss for the TSV is caused mainly by the material loss of the Silicon (Si) substrate due to its low resistivity. However, at millimetre wave (mmWave) frequency range, especially above 50GHz, in addition to the insertion loss, the return loss due to impedance mismatched becomes significant. These losses become a serious setback for the Si Interposer for the mmWave applications. To overcome these losses, polymer cavity formed in the Si substrate with TSV is developed. The polymer has lower loss tangent and lower dielectric constant than Si. These properties can help to reduce the insertion loss and the return loss. Depending on the requirement, multiple set of TSV can be formed on the polymer cavity to provide higher interconnect density. From the simulation results, the new polymer cavity TSV at 100GHz have an insertion loss and return loss of ∼0.2dB and less than −25dB, respectively. On the other hand, conventional high resistivity TSV has an insertion loss and return loss of ∼1.4dB and more than −10dB, respectively, at the same frequency. For higher frequency range, the performance of the polymer cavity TSV is approximately consistent, but the conventional TSV deteriorated drastically. In this paper, the design, fabrication process and the measurement results are presented. The prototype polymer cavity TSV via-line-via test vehicle has a measured insertion loss of less than 1dB and a return loss of better than −10dB through the frequency range up to 110Gz.

Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

Recently, Fan-out Wafer Level Packaging (FOWLP) has been emerged as a promising technology to meet the ever increasing demands of the consumer electronic products. However, conventional FOWLP technology is limited to small size packages with single chip and Low to Mid-range Input/ Output (I/O) count due to die shift, warpage and RDL scaling issues. In this paper, we are presenting new RDL-First FOWLP approach which enables RDL scaling, overcomes the die shift, die protrusion and warpage challenges of conventional FOWLP, and extend the FOWLP technology for multi-chip and high I/O count package applications. RDL-First FOWLP process integration flow was demonstrated and fabricated test vehicles of large multi-chip package of 20 x 20 mm2 with 3 layers fine pitch RDL of LW/LS of 2μm/2μm and ~2400 package I/Os. Two Through Mold Interconnections (TMI) fabrication approaches (tall Cu pillar and vertical Cu wire) were evaluated on this platform for Package-on-Package (PoP) application. Backside RDL process on over molded Chip-to-Wafer (C2W) with carrier wafer was demonstrated for PoP applications. Laser de-bonding and sacrificial release layer material cleaning processes were established, and successfully used in the integration flow to fabricate the test vehicles. Assembly processes were optimized and successfully demonstrated large multi-chip RDL-first FOWLP package and PoP assembly on test boards. The large multi-chip FOWLP packages samples were passed JEDEC component level test Moisture Sensitivity Test Level 1 & Level 3 (MST L1 & MST L3) and 30 drops of board level drop test, and results will be presented.

Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging

Fan-out wafer level packaging (FO-WLP) technology has lots of advantages of small form factor, higher I/O density, cost effective and high performance. However, wafer warpage is one big challenge during wafer process, which needs to be addressed for successful process integration. In this study, methodology to understand and reduce wafer warpage at different processes is presented in terms of geometry design, material selection, and process optimization through finite element analysis (FEA), theoretical calculation and experimental data. Quick wafer warpage evaluation method is proposed and compared with FEA results for the molded wafer. Wafer process dependent modeling is established and results are validated by experimental data for both mold-first and RDL-first methods. Key parameters are identified based on FEA modeling results: thickness ratio of die to total mold thickness, compression molding condition, molding compound and support wafer materials, dielectric material and Cu RDL design.

Process and reliability assessment of 200μm-thin embedded wafer level packages (EMWLPs)

In this paper, we focus how to overcome process challenges, such as die shift and warpage, and to fabricate thin embedded wafer level packages (EMWLPs) with 200μm-thick eventually. The initial warpage of reconfigured wafer after post mold curing (PMC) was about 1.0 ∼ 1.4mm range. After PMC, the molded wafer was background to 200μm thickness and redistribution layer (RDL) process was conducted on both front- and back-sides of the molded wafer sequentially. However, the warpage increased up to several mm during 1st RDL formation so that multi-RDLs process could not be performed due to the largely warped wafer. In order to overcome the large warpage issue, thick Si wafer was adopted as a carrier and the molded wafer was bonded on the Si carrier before RDL process. The measured warpage values decreased from several mm to about 500μm during RDL process by using the Si carrier and two RDLs were fabricated on both sides of the molded wafer. Consequently, the fabrication of 200μm-thick molded wafer for EMWLPs was successfully achieved. Three reliability tests (MSL3, HAST, and TC) were performed with singulated EMWLP modules and no failure was observed in the results of component level reliability. Furthermore, for in-depth understanding of the effects of MCs and carrier types on the die shift of the reconfigured wafer, the die shift values were measured on the molded wafers made of different MCs and different carriers as well. The experimental results are being compared with computational simulation and this can provide basic guidance of material selection and molding process.

Development of low profile fan out PoP solution with embedded passive

Currently PoP (Package on Package) has become a main stream of 3D integration for logic devices such as baseband and application processors with high performance memory in mobile application. This PoP has an advantage of a smaller package size with high functionality due to stacking of two different packages. However a conventional PoP with PCB substrate has a limitation to meet the recent requirement of a low profile with high performance in the thin mobile application. A fan out wafer level packaging is one of promising solution to meet a low profile with high performance. The direct solder attach on the RDL layer in the wafer level package provide a low profile package and RDL formation beyond Si die area provide a high performance with allowing higher solder ball counts. Also an embedded passive into fan out wafer level package is able to provide the better performance as well as flexibility to extend to SiP (System in Package). In this study, a low profile fan out Package on Package was successfully demonstrated with 14.0×14.0mm of a bottom package and 8.0×8.0mm of top package as well as embedded passives. The top and bottom package were electrically connected through TMV (Through Mold Via) with electro-less plating. TMV (Through Mold Via) was characterized with various EMC materials such as filler size, contents and resin material. The optimization of passive component location in term of process and reliability was performed using mold flow simulation. Also an assembly process was developed to minimize the package warpage using thermo-mechanical simulation.

Underfill characterization for multi-layer 3D-SiP stacked chip package

In this paper, evaluation of underfill materials for 3D SiP packages where micro bump interconnections and solder bumps has been presented. Characterization of underfill materials was carried out in terms of adhesion testing on various chip passivation surfaces and process optimization for void free filling. Capillary underfill materials have been evaluated for micro bump interconnections for 3D stacked module with different size chips as well as 3D stacked module with same size chips, and moldable underfill has been evaluated for over molding of stacked module along with underfilling of solder bump interconnections. Die shear test was carried out on adhesion test samples and results revealed failure between chip and polyimide layers in polyimide samples, and mixed failure between underfill and passivation layer in SiN samples. Process optimization for void free underfilling for CUFs were carried out based on dispensing temperature, speed, length, pattern and effects of plasma treatments. For MUF, the transfer molding process optimization was carried out by varying transfer time and die temperature to achieve void free underfilling and molding process. CSAM and through scan analysis was carried out on the under filled samples to check the quality of the underfilling process. The optimized process results shown void free underfilling for both 3D stacked module packages with different size chips as well as same size chips.

Thermo-mechanical reliability study on Package on Package (PoP) with Embedded Wafer Level Package (eWLP)

In order to improve the reliability of the proposed test vehicle of the Package on Package (PoP) with Embedded Wafer Level Package (eWLP) using through mold via (TMV) as vertical interconnect. In this paper, the solder joint reliability of eWLP PoP package was studied by the thermo-mechanical finite element simulation under the -40 °C to 125 °C thermal cycle loading conditions. The simulation results show that the critical solder ball is located at the diagonal corner solder ball of the bottom package. The effects of the structural parameters were indentified. The results show that the solder joint reliability can be enhanced by increasing the diameter and standoff of the solder ball, and reducing the overmold thickness of bottom package. Only using appropriate underfill and corner adhesive can enhance the reliability of solder ball. The underfill and corner adhesive material which are benefit to the solder ball reliability under thermal cycle loading were indentified and selected by the simulation.

Assembly of large dies fine pitch Cu/low-k FCBGA package with through silicon via (TSV) interposer

To eliminate the process of stacked with wire bonding interconnection technology, a through via silicon interposer which is used in stacked dies flip chip are assembled in this study currently. In this study, stack assembly process sequence and the sequence effect on solder joints formation 2nd level joints (between interposer chip and substrate) will be presented. 2nd level joints will be compared between 1x reflow and 2x reflow process. Underfill materials selection for stacked dies large chip package is established with Aluminum test vehicle without voids and delamination. Some warpage measurement was carried out on the underfilled package. The optimized underfill process was implemented on the actual cu/low-k test vehicle with through silicon via interposer. Effect of different flux type on the bump voids formation will be discussed. Achieved good assembly yield with optimized flip chip process flow, using selected flux in different flip chip bonders.

Process and Reliability of Large Fan-Out Wafer Level Package Based Package-on-Package

This paper presents, the development of large multi-chip fan-out wafer level package (FOWLP) based Package-on-Package (PoP) using mold-First FOLWP integration flow for mobile applications. As part of this development, conventional mold-First FOWLP wafer reconstruction process has been optimized and selected key materials to overcome the challenges such as die shift, die protrusion, warpage. Fine pitch multi-layer RDL of LW/LS of 5µm/5µm fabrication, through mold via (TMV) formation, thin wafer handling for backside RDL and PoP assembly processes were also optimized. TMV process using laser drilling and sidewall plated Cu with polymer filling has been demonstrated. Using these optimized processes multi-chip FOWLP of 15 mm × 15 mm with double side RDL and high I/O count ~1360 I/Os at 400µm pitch was successfully demonstrated. Assembly process flow was optimized for PoP assembly on test boards, and build the PoP samples for reliability testing. FOWLP PoP samples were passed component level tests like MST L1, MST L3, HAST, MST L1+TC and board level tests 500 TCOB cycles and 30 drops of board level drop test.

Drop Impact Reliability Test and Failure Analysis for Large Size High Density FOWLP Package on Package

Drop test reliability of the 20 mm × 20 mm RDL-first FOWLP on bottom and 8 mm × 8 mm WLCSP on top for Package on Package (PoP) test vehicle was validated by the experimental testing in this paper. The results show that the built up PoP test vehicle can pass 30 times of drop impact test and some samples can pass 200 times drop impact test with the loading of 1500 G/0.5 ms. The failure mechanisms of Cu pad peeling off, cracking of dielectrics and Cu trace of the bottom RDL-first FOWLP and cracking on package corner solder joints of top WLCSP were identified by cross section observation. The peeling stress level on the solder joint and dielectrics layer were investigated by the dynamic explicit nonlinear drop impact simulation.