Chong Ser Choong

A novel electrically conductive wafer through hole filled vias interconnect for 3D MEMS packaging

A wafer through hole filled via interconnection method on silicon has been developed for 3D wafer level packaging for MEMS (Micrc-Electro mechanical systems) application. In this 3D package the bottom wafer is a MEMS device and the cap wafer is silicon. Using Deep Reactive Ion Etching process the through hole via has been formed on the silicon cap wafer. A conductive material is uniformly deposited on the backside of the cap wafer before the via etch process to serve as an etch stop layer in DRIE (Deep Reactive ion Etching) process. The cap wafer vias are filled with a conducting material by means of electroplating process. The seed metal is usually an UBM (Under bump metallization) layer which is subsequently pattemed to form bond pads on both top and bottom wafers. These two wafers are then aligned and bonded with soldedmetal to form a hermetically sealed wafer level package. Altemate methods are also investigated for plugging the via holes with conducting material and the process has been explained.

A Vertical Wafer Level Packaging using Through Hole Filled Via Interconnects by Lift Off Polymer Method for MEMS and 3D Stacking Applications

A vertical wafer level packaging for MEMS has been developed with through hole filled via interconnects. Through hole filled via interconnects are formed on a cap wafer by electroplating method and bonded to the MEMS using wafer to wafer bonding method. A bottom up approach electroplating method is used for filling the through hole via interconnect. In the bottom up approach, a handler wafer is used for seed layer formation and the same time for the filling the via. Through hole vias are formed on a cap wafer by DRIE (Deep Reactive Ion Etching) method and the insulation and barrier layers are formed to isolate the silicon wafer. A lift off polymer is coated on a handler wafer and the seed layer is deposited on the polymer. The through hole via wafer and the handler wafer is bonded together using photo resist and is subjected to electroplating process. The handler wafer is separated from the through hole filled wafer by a combination of polymer lift off and ultrasonic agitation method. The completed through hole via filled wafer can be a device wafer or normal silicon wafer. This wafer can also be a cap wafer for MEMS wafer level packaging application and for 3D stacking applications

Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

Recently, Fan-out Wafer Level Packaging (FOWLP) has been emerged as a promising technology to meet the ever increasing demands of the consumer electronic products. However, conventional FOWLP technology is limited to small size packages with single chip and Low to Mid-range Input/ Output (I/O) count due to die shift, warpage and RDL scaling issues. In this paper, we are presenting new RDL-First FOWLP approach which enables RDL scaling, overcomes the die shift, die protrusion and warpage challenges of conventional FOWLP, and extend the FOWLP technology for multi-chip and high I/O count package applications. RDL-First FOWLP process integration flow was demonstrated and fabricated test vehicles of large multi-chip package of 20 x 20 mm2 with 3 layers fine pitch RDL of LW/LS of 2μm/2μm and ~2400 package I/Os. Two Through Mold Interconnections (TMI) fabrication approaches (tall Cu pillar and vertical Cu wire) were evaluated on this platform for Package-on-Package (PoP) application. Backside RDL process on over molded Chip-to-Wafer (C2W) with carrier wafer was demonstrated for PoP applications. Laser de-bonding and sacrificial release layer material cleaning processes were established, and successfully used in the integration flow to fabricate the test vehicles. Assembly processes were optimized and successfully demonstrated large multi-chip RDL-first FOWLP package and PoP assembly on test boards. The large multi-chip FOWLP packages samples were passed JEDEC component level test Moisture Sensitivity Test Level 1 & Level 3 (MST L1 & MST L3) and 30 drops of board level drop test, and results will be presented.

Comprehensive Study on the Interactions of Multiple Die Shift Mechanisms During Wafer Level Molding of Multichip-Embedded Wafer Level Packages

Comprehensive numerical and experimental analyses were performed to investigate the issue of die shift during the 12-in wafer level molding process of multichip-embedded wafer level packages. The proposed modeling methodology considers the major mechanical and mold flow mechanisms in the phenomenon. Experimental characterization of the adhesion behavior of a die attached on mold tape at molding temperature suggests that mold tape behavior is an important contributing factor to die shift and the mold tape behavior at high temperature needs to be considered for improved die shift prediction. Incorporating the characteristics of the mold tape adhesion behavior, the die shift obtained from the improved numerical model is compared with the experimental observations and a good correlation is observed. From the investigation, it was found that mechanical effects such as coefficient of thermal expansion of the mold plate and chemical shrinkage can contribute up to 85% of the die shift while fluidic force accounts for the rest.

Challenges and approaches of TSV thin die stacking on organic substrate

The requirements for high density packaging such as smaller form factor, high performance and multi functionality electronics products have resulted in electronics industry moving towards 3D System in package technology (3D SIP). Some of the main advantages of 3D SIP packaging are high volume applications, smaller form factor, better connectivity between components in a 3D package, lower noise, lower power consumption and higher operating frequencies [1]. A 3D package is a cost effective solution as it helps to save placement and routing area on board using several IC process in the same module. A stacked die SiP package offers flexibility in combining die from different fab processes into a single package. Board area savings are realized by stacking the die vertically vs a side by side approach. This package technology is mainly used where X-Y size constraint is the critical requirement. Some of the key technologies needed to enable chip stacking include silicon through-vias and high-density lead-free interconnects [2]. In the paper, 2 different reflow approaches are used for the 3 die stacked flip chip assembly (i) sequential reflow and (ii) 3 die stacked simultaneous reflow. The effect of the reflow approaches of the stacked die assembly with TSV on die warpage, solder wetting, solder voids and bonding alignment is addressed in this paper. In addition, a simple D.O.E was conducted to understand the effect of bond force on thin die stacked assembly Pb-free microbumps is also reported. Results showed that optimum bond force is important to ensure no die cracks during flip chip bonding for 3 layer stacked die. In addition to the DOE conducted to understand the effect of bonding parameters on thin stacked die assembly, the selection of flux in terms of flux tackiness, flux for good solder wetting and minimum solder voids in the flip chip assembly were also addressed in this work. Low standoff for microjoint assembly often poses a challenge for underfill dispensing process. The standoff between the microbump joint of the chip on chip flip chip bonding is usually about 15µm to 20µm. The dispensing space is tight and often with limitations on the area where underfill fluids can be dispensed. Therefore it is important to evaluate flowability, bleeding of the underfill and the void formation in the underfill for stacked die assembly. The impact of these various factors on the stacked die assembly was discussed in this paper. Finally moldable underfill is then used to encapsulate the 3 layer stacked chip on the substrate.

Thermal modeling and simulation of a package-on-package embedded micro wafer level package (EMWLP) structure at the package and system-level

In the embedded wafer-level packaging field, the embedded micro wafer level package (EMWLP) technology leverages on fan-out redistribution connections, keeping the reliance on wire-bonding and flip-chip bump connections to a minimum, thus streamlining the packaging process. As the embedded micro wafer level packaging (EMWLP) technology evolves to capitalize on package-on-package (POP) technology, this studys parametric thermal modeling focuses on analyzing the thermal impact of increased density in a low thermal conductivity packaging material. The package design in this work has the following specifications: the memory EMWLP (die size: 7×7×0.2mm) on logic EMWLP structure (die size : 8×8×0.2mm), sized 12×12×0.9mm in total. The POP structure, furthermore, incorporates through-mold-interconnects (TMI) in the bottom logic package to provide short electrical connection from the top package to the board level. The impact on multi-package thermal resistance is then studied as the following parameters vary: power dissipation (in both packages); mold conductivity; number of TMIs; number of solder ball connections; inclusion and size of an interpackage heatslug; inclusion and thermal conductivity of a top heatspreader. The thermal management of the dies are also studied based on the above measures and was found to accommodate under 4W of total POP power. Finally, simulation results for a general system-level thermal modeling of the EMWLP POP in a cellphone scenario are also conducted with passive thermal management solutions proposed.

Package-level thermal management of a 3D embedded wafer level package

As the embedded wafer-level packaging (eWLP) technology evolves to capitalize on package-on-package (POP) technology, thermal analysis has been performed to investigate and improve the heat dissipation capability of the 3D package structure. 3D simulation models have been built to study the impact of the thermal properties (underfill material, passivation layer and mold compound) and geometries (over mold, passivation layer and Cu layer in RDL) on the package thermal performance. We also analyzed the thermal effect of the Cu percentage in each RDL layer. The top heat spreader, thermal via arry, bottom heat dissipation plate and two types of top thermal cases have employed to enhance the heat dissipation capability. In baseline conditions, without any enhancement structure, the 85°C temperature limit can be met, at a max total PoP power dissipation of 2W (Logic: 1.5W, memory: 0.5W). In the mobile device scenario, passive cooling solutions have been applied to the PoP structure, and a total power of 4W can be accommodated with the proposed cooling structures.

Heterogeneous Three-Layer TSV Chip Stacking Assembly With Moldable Underfill

This paper reports the study of 3-D die stacking of three chips through-silicon-via (TSV) interconnections. Two different reflow approaches were used for the three-die stacked flip-chip assembly: 1) sequential reflow and 2) three-die stacked simultaneous reflow. The effect of the reflow approaches of the stacked die assembly with TSV on die warpage, solder wetting, solder voids, and bonding alignment is addressed in this paper. A simple design of experiment was conducted to understand the effect of bond force on thin die stacked assembly and Pb-free microbumps. Results showed that optimum bond force is important to ensure no die cracks during flip-chip bonding for three-layer stacked die. The selection of flux in terms of flux tackiness, flux for good solder wetting, and minimum solder voids in the flip-chip assembly were also addressed in this paper. Low standoff for microjoint assembly often poses a challenge for underfill dispensing process. The standoff between the microbump joint of the chip-on-chip flip-chip bonding is usually ~15-20 μm. The dispensing space is tight and often with limitations on the area where underfill fluids can be dispensed. Therefore, it is important to evaluate the flowability, bleeding of the underfill, and void formation in the underfill for stacked die assembly. The impact of these various factors on the stacked die assembly is discussed in this paper. The reliability of a pyramidal shape three-layer stacked TSV die package was studied by both experiments and finite-element analysis (FEA). The originally designed microbumps were located peripherally around the edge of the die, which induces a concentrated bending force on the lower die when stacking the upper die. FEA simulation results showed that such bump design induces large stress and deflection in the lower die during die stacking process. A new bump layout design has been optimized with some dummy bumps added on the central area of the die to support bending force induced by die stacking. The new design significantly reduces die stress and deflection. A moldable underfill was then used to encapsulate the three-layer stacked chip on the substrate.

A novel compact antenna with a low profile demonstrated on embedded wafer level packaging (EMWLP) technology

In an RF front-end module, the reduction of the antenna size is a challenge since it is dependent on the frequency of operation. In this paper, a method of antenna miniaturization is introduced, by employing a novel meander CPWG feed structure as well as reducing the footprints of both radiating structure and the feed structure. In one of the proposed structures, the bandwidth can be enhanced by introducing a slotted ground plane for better matching. The structures are fabricated on cost-effective platforms using embedded wafer level packaging (EMWLP) and FR-4 laminates, with a compact footprint and low profile achieved.

Low temperature bonding studies of Au-studs and AuSn-solder bumps on Au-surface using ultrasonic energy

Conventional flip chip bonding requires heating process to enable solder to melt and electrically conductive adhesives to cure. Applying ultrasonic dose, successful flip chip bonding can be achieved at lower temperatures and bonding pressures. Using ultrasonic flip chip bonding is attractive as the reduction in bonding temperature reduces processing time, by reducing time taken for ramping up and cooling down of bonding arm in thermal compression; it also reduces the mismatch of coefficient of thermal expansion (CTE) between the chip and substrate during bonding compared to thermal compression bond and flux and reflow process. In this study, feasibility of room-temperature ultrasonic flip chip bonding of eutectic AuSn solder and Au-stud bumps was evaluated. Design of experiment was carried out on Argon and Hydrogen plasma process as a pre-flip chip cleaning treatment. Investigation of critical ultrasonic flip chip bonding parameters such as ultrasonic power, bonding force and chuck temperature was carried out. In the full manuscript, details of the experimental trials and results of room-temperature bonding of Au-studs and eutectic AuSn solder bumps on Au-surface would be discussed.