Lindsey H. Hall

Copper Deposition on HF Etched Silicon Surfaces: Morphological and Kinetic Studies

The kinetics and morphologies of Cu deposition on HF-treated silicon surfaces were investigated by atomic force microscopy (AFM), inductively coupled plasma mass spectroscopy (ICP/MS), and graphite furnace atomic absorption spectroscopy (GFAAS). The early stage (<60 s) of Cu deposition, as characterized by AFM, was found to be dominated by the nucleation of nanometer-sized Cu nuclei on HF-treated silicon surfaces. After 60 s of Cu deposition, the total grain number of Cu deposits was leveled to a constant plateau. However, a significant grain size increase of deposition Cu nuclei was noticed. We employed an AFM volume-integration technique in conjunction with the ICP/MS and GFAAS measurements to demonstrate that the Cu deposition rate was limited by the diffusion of Cu 2+ ions across the stationary solution layer toward the silicon surface.

Nucleation and Growth Behavior of Atomic Layer Deposited HfO2 Films on Silicon Oxide Starting Surfaces

Growing nanometer-thin HfO 2 films by atomic layer deposition (ALD) for implementation in advanced transistor structures is controlled by the density of reactive OH sites on the surface. The impact of thin SiO 2 starting surfaces, grown by wet chemical processes and by wetting a thermal oxide, on the nucleation and growth of ALD HfO 2 has therefore been evaluated. Our results demonstrate that both surface pretreatments display the same dependence of the initial HfO 2 growth on the interfacial layer thickness. This correlation is first characterized by a linear increase, which can be interpreted in terms of increasing OH surface concentration. Once an ellipsometric oxide thickness of approximately 0.8 nm is reached, saturation of the HfO 2 deposition occurs. Maximal OH coverage of the surface or steric hindrance of the adsorbed precursor molecules could explain this observation. However, the increased growth-per-cycle at lower deposition temperatures can be attributed to an improved hydroxylation of the surface, excluding steric hindrance as the primary factor causing saturation. Furthermore, electrical characterization revealed that both interfacial oxides show identical leakage scaling behavior down to an equivalent oxide thickness of 0.8 nm.

Silicon Orientation Effects in the Atomic Layer Deposition of Hafnium Oxide

The continuous downscaling of complementary metal oxide semiconductor devices demands the introduction of dielectric layers with a high permittivity K. Three-dimensional (3D) transistor structures, such as FinFET devices, require excellent step coverage by the high-K material as provided by atomic layer deposition (ALD). In addition, because of the 3D structure, surfaces with different crystallographic orientation need to be covered. Because the initial HfO 2 deposition using ALD HfCl 4 /H 2 O is governed by the OH surface density, we investigated its dependence on the crystallographic orientation of the silicon substrate. For oxidations in O 3 /H 2 O, a (110) orientated substrate oxidizes faster than silicon (100) up to a thickness of ∼0.7 nm as measured by X-ray photoelectron spectroscopy. Also, irrespective of the substrate orientation, the HfO 2 deposition is found to increase with increasing SiO 2 thickness and thus OH coverage of the surface. This implies that, for oxide thicknesses below0.7 nm, the oxidation of silicon (100) results in a thinner oxide and, hence, less HfO 2 deposition in comparison to silicon (110). However, these differences are marginal after implementation in transistor devices as is shown by their capacitance and mobility. As a result, for FinFET applications, a conformally deposited HfO 2 layer will be independent of the crystallographic substrate orientation.

TXRF Analysis of SC‐1 Treated Silicon Wafers

Silicon wafer cleaning is the most frequently applied processing step in the integrated circuit manufacturing sequence. This process is intended to remove several different types of contaminants, among them particles, metallics, and organics. It has been estimated, however, that over fifty percent of yield losses in integrated circuit manufacturing are caused by contamination remaining on the surface of silicon wafers after cleaning. It is the object of this article to document the effects of using improved, ultrahigh purity chemicals on silicon wafer surfaces as measured by total reflection x-ray fluorescence, TURF. During this study, silicon samples were cleaned with standard grade chemicals and ultrahigh purity chemicals, and metallic impurities were then measured with TURF. It was found that the use of ultrahigh purity chemicals substantially reduced the amount of surface contamination present on wafer surfaces after cleaning

A New Potentiometric Sensor for the Detection of Trace Metallic Contaminants in Hydrofluoric Acid

Detection of ultratrace levels of metallic ion impurities in hydrofluoric acid solutions was demonstrated using a silicon-based sensing electrode. The sensors operation principle is based on direct measurements of the silicon open-circuit potential shift generated by the charge-transfer reaction between metallic ions and the silicon-based sensing surface. For instance, the silicon-based sensor is capable of detecting parts per-trillion to parts-per billion level of Ag + ions in HF solutions with a detection sensitivity of ca. +150 mV shift per decade change of [Ag + ]. The new sensor can have practical applications in the on-line monitoring of microelectronic chemical processing.

Plasma Etch Processes for Embedded FRAM Integration

We describe the etch processes used for integration of embedded ferroelectric random access memory (FRAM) within a standard CMOS logic flow. The ferroelectric module is inserted following front-end contact formation and prior to backend integration using only two additional mask levels: capacitor pattern and bi-level via pattern. The single-mask stack etch process employs a TiAlN hardmask to define Ir/IrOx/PZT/IrOx/Ir capacitors. Protective sidewalls can be formed using an etchback process. The bi-level via etch and subsequent metal fill processes complete the FRAM module formation. Functional 4 MB arrays embedded with 5 levels of Cu/FSG integration have been demonstrated.

Ultrapure water quality monitoring by a silicon-based potentiometric sensor

A solid state silicon-based potentiometric sensor and a resistivity sensor were employed to monitor the water quality from an ultra-pure water production unit. A minute ionic impurity increase (at the low ppt level), which was not detectable by the conventional water resistivity sensor, can be sensitively detected by the silicon-based sensor. This slight degradation of water purity, independently confirmed by inductively coupled plasma mass spectrometry and atomic force microscopy, was attributed to early boil-off from the saturated water purification cartridge. The silicon-based sensor can potentially function as an ultra-sensitive monitoring sensor in conjunction with the conventional resistivity sensor to ensure water purity at parts per trillion level.

Atomic Layer Deposition of HfO2 on (100) and (110) Oriented Silicon Surfaces

The continuous need for enhanced performance of the integrated circuits demands for the development of new device structures other than the conventional planar MOSFET. Multi-gate transistors – such as the FinFET – are considered to overcome the technological challenges as they can be scaled down to very short gate lengths. Furthermore, scaling of the device dimensions requires the introduction of gate dielectrics with a permittivity κ, higher than that of SiO2. As the FinFET consists of a vertical silicon fin, the high-κ dielectric has to be deposited on silicon with both a (100) and (110) crystal orientation. Moreover, this substrate topology requires the use of a deposition technique that offers excellent conformality and step coverage of the as-grown material. These characteristics are ensured by using Atomic Layer Deposition (ALD) to grow the gate dielectric.