Lingquan Wang

Border traps in Al2O3/In0.53Ga0.47As (100) gate stacks and their passivation by hydrogen anneals

Charge-trapping defects in Pt/Al2O3/In0.53Ga0.47As metal-oxide-semiconductor capacitors and their passivation by hydrogen are investigated in samples with abrupt oxide/III-V interfaces. Tunneling of electrons into defect states (border traps) in the atomic layer deposited Al2O3 near the oxide/semiconductor interface is found to control the frequency dispersion of the capacitance in accumulation. Hydrogen anneals effectively passivate border traps in the oxide, in addition to some of the midgap states that control carrier generation in the channel. This is evident in the reduced frequency dispersion in accumulation, reduced capacitance-voltage stretch-out through depletion, and suppression of the inversion carrier response in capacitance-voltage measurements.

Scaling of Nanowire Transistors

This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.

An investigation of a nonspiking Ohmic contact to n-GaAs using the Si/Pd system

A low-resistance nonspiking Ohmic contact to n-GaAs is formed via solid-state reactions utilizing the Si/Pd/GaAs system. Samples with Si to Pd atomic ratios greater than 0.65 result in specific contact resistivity of the order of 10 −6 Ω cm 2 , whereas samples with atomic ratios less than 0.65 yield higher specific contact resistivities or rectifying contacts. Rutherford backscattering spectrometry, cross-sectional transmission electron microscopy, and electron diffraction patterns show that a Pd, Si layer is in contact with GaAs with excess Si on the surface after the Ohmic formation annealing. This observation contrasts with that on a previously studied Ge/Pd/GaAs contact where Ohmic behavior is detected after transport of Ge through PdGe to the interface with GaAs. Comparing the Ge/Pd/GaAs system with the present Si/Pd/GaAs system suggests that a low barrier heterojunction between Ge and GaAs is not the primary reason for Ohmic contact behavior. Low-temperature measurements suggest that Ohmic behavior results from tunneling current transport mechanisms. A regrowth mechanism involving the formation of an n + GaAs surface layer is proposed to explain the Ohmic contact formation.

Stable and shallow PdIn ohmic contacts to n-GaAs

A thermally stable, low‐resistance PdIn ohmic contact to n‐GaAs has been developed based on the solid phase regrowth mechanism [T. Sands, E. D. Marshall, and L. C. Wang, J. Mater. Res. 3, 914 (1988)]. Rapid thermal annealing of a Pd‐In/Pd metallization induces a two‐stage reaction resulting in the formation of a uniform single‐phase film of PdIn, an intermetallic with a melting point greater than 1200 °C. A thin (∼5 nm) layer of average composition In0.4Ga0.6 As uniformly covers the interface between the PdIn layer and the GaAs substrate. Specific contact resistivities and contact resistances of ∼1×10−6 Ω cm2 and 0.14 Ω mm, respectively, were obtained for samples annealed at temperatures in the 600–650 °C range. The addition of a thin layer of Ge (2 nm) to the first Pd layer extends the optimum annealing temperature window down to 500 °C. Specific contact resistivities remained in the low 10−6 Ω cm2 range after subsequent annealing at 400 °C for over two days.

Low‐resistance nonspiking ohmic contact for AlGaAs/GaAs high electron mobility transistors using the Ge/Pd scheme

Nonspiking (nonalloyed) Ge/Pd ohmic contact formed via solid phase reaction on an AlGaAs/GaAs high electron mobility transistor (HEMT) was investigated. The surface morphology of the Ge/Pd contact is smooth and planar with a typical contact resistivity of about 3×10−7 Ω cm2. The current‐voltage characteristics of the HEMTs with the Ge/Pd contacts are similar to those with the conventional AuGe/Ni spiking (alloyed) contacts. Since only a thin substrate surface layer of 100–200 A was reacted with the Ge/Pd contact, we can conclude that ohmic contacts can be made to the two‐dimensional electron gas without deep penetration of the metallization. This observation is in agreement with the concept that transport due to tunneling is significant across heterojunctions. The Ge/Pd contact may be potentially useful in HEMT integrated circuit technology.

An investigation of the Pd‐In‐Ge nonspiking Ohmic contact to n‐GaAs using transmission line measurement, Kelvin, and Cox and Strack structures

The Pd‐In‐Ge nonspiking Ohmic contact to n‐GaAs has been investigated using the transmission line, the Kelvin, and the Cox and Strack structures. It has been found that a layered structure of Pd/In/Pd/n‐GaAs with 10–20 A of Ge imbedded in the Pd layer adjacent to the GaAs can lead to a hybrid contact. When the Ohmic formation temperature is above 550 °C, a layer of InxGa1−xAs doped with Ge is formed between the GaAs structure and the metallization. When the Ohmic formation temperature is below 550 °C, a regrown layer of GaAs also doped with Ge is formed at the metallization/GaAs interface. The contact resistivity of 2–3×10−7 Ω cm2 for this contact structure is nearly independent of the contact area from 900 to 0.2 μm2. Low‐temperature Ohmic characteristics and thermal stability are also examined.

III–V FET channel designs for high current densities and thin inversion layers

III–V FETs are being developed for potential application in 0.3–3 THz systems and VLSI. To increase bandwidth, we must increase the drive current I<inf>d</inf> = qn<inf>s</inf> v<inf>inj</inf>W<inf>g</inf> per unit gate width W<inf>g</inf>, requiring both high sheet carrier concentrations n<inf>s</inf> and high injection velocities v<inf>inj</inf>. Present III–V NFETs restrict control region transport to the single isotropic Γ band minimum. As the gate dielectric is thinned, I<inf>d</inf> becomes limited by the effective mass m*, and is only increased by using materials with increased m* and hence increased transit times.¹ The deep wavefunction also makes Γ -valley transport in low-m*materials unsuitable for < 22-nm gate length (L<inf>g</inf>) FETs. Yet, the L-valleys in many III–V materials² have very low transverse m<inf>t</inf> and very high longitudinal mass m<inf>1</inf>. L-valley bound state energies depend upon orientation, and the directions of confinement, growth, and transport can be chosen to selectively populate valleys having low mass in the transport direction^3,4. The high perpendicular mass permits placement of multiple quantum wells spaced by a few nm, or population of multiple states of a thicker well spaced by ∼10–100 meV. Using combinations of Γ and L valleys, n<inf>s</inf> can be increased, m* kept low, and vertical confinement improved, key requirements for <20-nm L<inf>g</inf> III–V FETs.

Backside secondary ion mass spectrometry study of a Ge/Pd ohmic contact to InP

High‐resolution SIMS (secondary ion mass spectrometry) depth profiles of Ge/Pd ohmic contacts on InP are obtained by sputter‐etching from the back (semiconductor) side. The samples contain an InGaAs‐etch stop layer, to allow chemical thinning, and InGaAsP marker layers, which allow alignment and calibration of the depth profiles on the nm scale. At 200 °C, a Pd‐In‐P alloy layer is observed to form at the contact interface. The thickness of this layer is dependent on the amount of metallic Pd available for reaction. Subsequent processing at 325 °C results in the partial dissolution of this alloy layer, as PdGe forms at the contact interface, and regrowth of the liberated InP. Ge is detected in the regrown region but is not observed to diffuse into the substrate. Ge epitaxy is not observed at the contact interface at 325 °C, in contrast to the behavior of the Ge/Pd‐GaAs contact. The experimental evidence suggests that regrowth is a key step in the formation of the ohmic contact.

Nonspiking ohmic contact to p‐GaAs by solid‐phase regrowth

A low‐resistance and nonspiking contact consisting of a layered structure of Si/Ni(Mg) on p‐GaAs is formed by solid‐phase regrowth. Backside secondary‐ion mass spectrometry and cross‐sectional transmission electron microscopy show an initial reaction between Ni and GaAs to form NixGaAs which is later decomposed to form NiSi by reacting with the Si overlayer. This reaction leads to the solid‐phase epitaxial regrowth of a p+ ‐GaAs layer doped with Mg. The total consumption of substrate is limited to a few hundred angstroms. The as‐formed ohmic contact structure is uniform and planar with an average specific contact resistivity of ∼7×10−7 Ω cm2 on substrates doped to 8×1018 cm−3. The thermal stability of this contact scheme is also reported.

The Si/Pd(Si,Ge) ohmic contact on n‐GaAs

A modified Si/Pd ohmic contact to n‐GaAs has been developed based on the solid‐phase regrowth mechanism. The Si/Pd contact usually yields a contact resistivity of 2×10−6 Ω cm2. A thin (∼15 A) layer of additional Ge or Si embedded in the Pd layer of the Si/Pd contact structure is used to reduce the contact resistivity from ∼2×10−6 to 2–4×10−7 Ω cm 2 without suffering from a loss of thermal stability. The reduction in the contact resistivity is explained in terms of the formation of an n+ GaAs surface layer via solid‐phase regrowth. The modified contacts show uniform surface and interface morphologies. The contact resistivity of the modified contacts remains in the mid‐10−6 Ω cm2 range after annealing at 400 °C for 50 h.