Lionel Damez

Design of a Scalable Network of Communicating Soft Processors on FPGA

In this work we investigate the implementation of a general parallel architecture using platform FPGA. With the implementation of communicating multiple soft processors mapped over a hypercube topology, our objective is to determine platform FPGA and SoC design environment advantages and limits for scalable multiple processors conception. We investigate the effect of communication system in FPGA devices, experimenting with different designs decisions. We present some performance results with the illustration of a parallel sort algorithm.

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.

SIMD, SMP and MIMD-DM parallel approaches for real-time 2D image stabilization

We present a real-time image stabilization method, based on a 2D motion model and different levels of parallel implementation. This stabilization method is decomposed into three main parts. First, the image matching is determined by a feature-based technique, then the motion between consecutive frames is estimated and filtered to extract the unwanted motion component. This component is finally used to correct (warp) the images, resulting in a stable sequence. To validate our stabilization approach in a real-time on-board system context, the algorithm was implemented and tested over different hardware platforms, allowing a performance evaluation in function of the adopted architecture. In this paper, we present some of the results, concerning the parallel implementation of the algorithm, using the MW ALTIVEC/spl reg/ instructions set, a symmetric multi-processor (SMP) architecture and MIMD-DM architecture.

Embedding of a Real Time Image Stabilization Algorithm on SoPC Platform, a Chip Multi-processor Approach

Highly regular multi-processor architecture are suitable for inherently highly parallelizable applications such as most of the image processing domain. System on a programmable chip (SoPC) allows hardware designers to tailor every aspects of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of core, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirement and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs. We present both software and hardware implementation with performance results on a Xilinx SoPC target.

A generic MP-SoC design methodology for the fast prototyping of embedded image processing

This article proposes an original methodology for the fast prototyping of image processing on a generic MP-SoC (Multi-Processors System on Chip) architecture. To define a processors network adapted to a particular application is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability of an ad hoc design methodology. This paper illustrates a new methodology that enables to instantiate a generic Homogeneous Network of Communicating Processors (called HNCP) tailored for a targeted application. The HNCP is generated with a tool that avoids fastidious manual editing operations for the designer. Specific lightweight communication functions have been developed to fasten the programming of the MP-SoC network. A case study (image texture analyzes) is presented to illustrate the proposed MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

Fast prototyping of complex Signal and Image Processing applications on SoC using homogenous network of communicating processors

We present a new methodology for the embedding of signal and image processing applications on integrated electronic circuits, such as SoPCs or SoCs. With the proposed general methodology, we present the basic hardware concepts, focusing on communication subsystem design.