Loic Sieler

A scalable and embedded FPGA architecture for efficient computation of grey level co-occurrence matrices and Haralick textures features

This paper presents a novel and optimized embedded architecture based FPGA for an efficient and fast computation of grey level co-occurrence matrices (GLCM) and Haralick textures features for use in high throughput image analysis applications where time performance is critical. The originality of this architecture allows for a scalable and a totally embedded on Chip FPGA for the processing of large images. The architecture was implemented on Xilinx Virtex-FPGAs without the use of external memory and/or host machine. The implementations demonstrate that our proposed architecture can deliver a high reduction of the memory and FPGA logic requirements when compared with the state of the art counterparts and it also achieves much improved processing times when compared against optimized software implementation running on a conventional general purpose processor.

A MP-SoC design methodology for the fast prototyping of embedded image processing system

This article proposes an original design flow for the fast prototyping of image processing on a MP-SoC (MultiProcessors System on Chip) architecture. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve highperformance customized solutions. The effectiveness of such approaches largely depends on the availability of an ad hoc design methodology. This paper illustrates a new design flow that enables to instantiate a generic Homogeneous Network of Communicating Processors (called HNCP) tailored for a targeted application. The HNCP is generated with a tool that avoids fastidious manual editing operations for the designer. Specific lightweight communication functions have been developed to fasten the programming of the MP-SoC network. A case study (image texture analyzes) is presented to illustrate the proposed MP-SoC design methodology and enables to focus on architecture exploration, instantiated scheme of parallelization and timing performance.

Embedding of a real time image stabilization algorithm on a parameterizable SoPC architecture a chip multi-processor approach

Highly regular multi-processor architectures are suitable for inherently highly parallelizable applications such as most of the image processing domain. Systems embedded in a single programmable chip platform (SoPC) allow hardware designers to tailor every aspect of the architecture in order to match the specific application needs. These platforms are now large enough to embed an increasing number of cores, allowing implementation of a multi-processor architecture with an embedded communication network. In this paper we present the parallelization and the embedding of a real time image stabilization algorithm on a SoPC platform. Our overall hardware implementation method is based upon meeting algorithm processing power requirements and communication needs with refinement of a generic parallel architecture model. Actual implementation is done by the choice and parameterization of readily available reconfigurable hardware modules and customizable commercially available IPs (Intellectual Property). We present both software and hardware implementation with performance results on a Xilinx SoPC target.

Configurable and high-throughput architectures for Quasi-cyclic low-density parity-check codes

LDPC codes are currently the most promising coding technique to achieve the Shannon capacity, making them very popular in modern telecommuncation applications. Despite the attractivity stemming from their effectiveness, encoding and decoding LDPC codes is a rather complex task, due to the size and structure of the codes, especially when considering the ever increasing need for higher throughput in communication networks. All these constraints are setting the demand for new encoding/decoding architectures very high. In this paper, we propose effective encoder and decoder architectures for the Quasi-Cycle subclass of LDPC codes. The main features being targeted are pre-synthesis configurability and high throughput. QC-LDPC codes exhibit a highly regular structure in their parity check matrices making easier the design process to obtain the high levels of architectural parallelism necessary to achieve the required high throughputs. In order to validate our design, several encoder and decoder were implemented on FPGAs of the Altera Stratix III and Xilinx Virtex4 using different code parameters (block length and code rate) for QC-LPDC codes from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.1 In) protocols. Throughputs up to 32 Gbits/s and 732 Mbits/s have been achieved for the encoder and decoder, respectively.

A high throughput configurable parallel encoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes

In this paper, we are proposing a new architecture for fast encoding of Quasi-Cyclic Low-Density Parity Codes (QC-LDPC). QC-LDPC codes are becoming more and more popular in a wide range of applications, including data transmission (WiMAX, DVB-S2) in telecommunication systems, increasing the need for effective encoder architectures. In our approach, support for a large subset of QC-LDPC codes is provided thanks to the configurability of the architecture at synthesis level. High levels of parallelism can be reached, and hence high throughput achieved, due to the modular encoder architecture that takes advantage of the highly regular structure of QC-LDPC parity check matrices. The architectural design has been validated through implementation on an Altera Stratix II FPGA of different encoders related to DVB-T2 and DVB-S2. Very high data rates (up to 28.9 GB/s) have been achieved with still acceptable hardware consumption (about 32k logic elements) proving the effectiveness of the approach.

Reaction time and physiological signals for stress recognition

Abstract This paper investigates the potential of stress recognition using the data from heterogeneous sources. Not only physiological signals but also reaction time (RT) is used to recognize different stress states. To acquire the data related to the stress of an individual, we design the experiments with two different stressors: visual stressor (Stroop test) and auditory stressor. During the experiments, the subjects perform RT task. Three physiological signals, Electrodermal activity (EDA), Electrocardiography (ECG) and Electromyography (EMG) as well as RTs are recorded. We develop the classifier based on the Support Vector Machines (SVM) for the stress recognition given the physiological signals and RT respectively. An overall good recognition performance of the SVM classifier is obtained. Besides, we present the strategy of recognition using the decision fusion. The recognition is thus achieved by fusing the classification results of physiological signals and RT with the voting method and a further improvement of recognition accuracy is observed. Results indicate that RT is efficient for stress recognition and the fusion of physiological signals and RT can bring in a more satisfied recognition performance.

VHDL-AMS electro-thermal modeling of a lithium-ion battery

Li-ion rechargeable batteries present an useful energy, low battery effect, and slow Self-discharge loss of charge when not in use. In this paper, we describe a VHDL-AMS model describing coupled electrical and thermal behaviors of a Li-Ion cell. This model relies on the experimental extraction of real characteristic parameters by using an efficient and low-cost test bench. Therefore, it allows to predict the realistic voltage variations by taking into account the state of charge and heating of the Li-ion cell, in order to design a battery system according the required capacity and electric power for the current electrical applications.

A generic packet router IP for multi-processors network-on-chip

In this paper, a generic IP is proposed to ensure communication for a Multi-Processors System on Chip (MPSoC) architecture. It is based on a specific hardware router and its associated Direct Memory Access (DMA) module. This scalable IP makes the instantiation easier and faster in MPSoC systems based on hypercube topology. Besides the hardware description, this work also presents the software layer and the communication functions developed to help the parallel programming based on functional skeletons. Implementation results are given regarding processing time, area and processor number on a Virtex 6 Xilinx FPGA target.

Dedicated wavelet QRS complex detection for FPGA implementation

The QRS complex is the most significant segment in the Electrocardiography (ECG) signal. By detecting its position, we can learn the physiological informations of the subjects, e.g. heart rate. In this paper, we propose a FPGA architecture for QRS complex detection. The detection algorithm is based on Integer Haar Transform (IHT). Due to its integer nature, the IHT avoids the floating point calculations and thus can be easily implemented in FPGA. The FPGA Cyclone EP3C5F256C6 is used as the target chip and all the components of the system are implemented in VHSIC Hardware Description Language (VHDL). The testing results show that the proposed FPGA architecture can achieve an efficient detection performance where the total detection accuracy exceeds 98%. Meanwhile, the FPGA implementation shows good design efficiency in the term of silicon consumption. Only 8% silicon resources of the target chip are occupied. The proposed architecture will be adopted as a core unit to make a FPGA system for stress recognition given the heterogeneous data.

Digital Implementation of an Improved LTE Stream Cipher Snow-3G Based on Hyperchaotic PRNG

SNOW-3G is a stream cipher used by the 3GPP standards as the core part of the confidentiality and integrity algorithms for UMTS and LTE networks. This paper proposes an enhancement of the regular SNOW-3G ciphering algorithm based on HC-PRNG. The proposed cipher scheme is based on hyperchaotic generator which is used as an additional layer to the SNOW-3G architecture to improve the randomness of its output keystream. The objective of this work is to achieve a high security strength of the regular SNOW-3G algorithm while maintaining its standardized properties. The originality of this new scheme is that it provides a good trade-off between good randomness properties, performance, and hardware resources. Numerical simulations, hardware digital implementation, and experimental results using Xilinx FPGA Virtex technology have demonstrated the feasibility and the efficiency of our secure solution while promising technique can be applied to secure the new generation mobile standards. Thorough analysis of statistical randomness is carried out demonstrating the improved statistical randomness properties of the new scheme compared to the standard SNOW-3G, while preserving its resistance against cryptanalytic attacks.