Patrick Loumeau

VHDL-AMS behavioral modelling and simulation of high-pass delta-sigma modulator

High-pass /spl Delta//spl Sigma/ modulator has the advantage of immunity from the low frequency noise and is thus very effective in the parallel architectures. In this paper, we present the behavioral modelling and simulation of /spl Delta//spl Sigma/ modulators in VHDL-AMS, and in particular of the high-pass modulator. A set of models in VHDL-AMS suitable for time-domain behavioral simulation of SC /spl Delta//spl Sigma/ modulators is developed. The proposed set of models takes into account at the behavioral level most of SC /spl Delta//spl Sigma/ modulator nonidealities, such as jitter noise, kT/C noise, 1/f noise, amplifier noise, switch nonidealities, amplifier nonidealities, and capacitor mismatch. We elaborate then a top-down design methodology that is validated by the measurement results.

Temporel and spectral analysis of time interleaved high pass sigma delta converter

Delta sigma modulators are widely used for low to moderate rate analog-to-digital conversion. But they are not adapted to high rate conversion because of time oversampling requirement. Parallel architecture is a potential solution to increase the frequency range of /spl Delta//spl Sigma/ ADC, especially the time-interleaved high-pass /spl Delta//spl Sigma/ converter. In this paper, we analyze the immunity from low-frequency offered by the high-pass /spl Delta//spl Sigma/ modulators in time-interleaved /spl Delta//spl Sigma/ ADC. The high-pass /spl Delta//spl Sigma/ modulators not only retains the performance of the converter and eliminates low frequency noise, but also allows simple adaptive channel gain equalization scheme to minimize channel gain mismatch effects by using LMS algorithm.

Non-uniform sampling schemes for IF sampling radio receiver

The IF sampling radio receiver based on the non-uniform sampling (NUS), technique is promising and would be a candidate for the multistandard reception. This technique allows the IF down-conversion and permit to eliminate or alleviate the anti-aliasing filter. For wideband and multistandards design, the choice of sampling rates for bandpass sampling is flexible. This paper introduces the NUS theory, particularly its random processes schemes; the additive random sampling (ARS) and the jittered random sampling (JRS). Then, it proposes the IF NUS receiver architecture. The reconstruction algorithm RA block represents the object of the comparison between the sampling schemes. Finally, validation of the algorithm, its anti-aliasing specificity and some simulation results are presented

Direct delta-sigma receiver: Analysis, modelization and simulation

This paper presents a model of direct delta-sigma receiver (DDSR) and methodology for theoretical transfer function (TF). The theoretical analysis is carried out by modeling the key elements of the DDSR, including the N-path filter, down-conversion mixer, baseband delta sigma modulator (DSM) and FIRDACs in order to optimize the loop filter coefficients. The contribution of different noise sources and the impact of the nonlinearities are also analyzed. The obtained simulation results show the accuracy of the proposed models and method. This top-down approach allows the designer to determine the key parameters for DDSR in terms of noise contributions, nonlinearity impacts, filtering effects as well as gain distribution and thus enables the optimization of the whole receiver. Although this methodology was applied to the conventional DDSR, but it can be used for any receiver architecture based on DDSR.

Nonuniformly Controlled Analog-to-Digital Converter for SDR Multistandard Radio Receiver

A new multistandard radio receiver architecture is presented to take advantage of nonuniformly controlled analog-to-digital converters (ADCs). By defining the statistical parameter related to the random sampling frequency, a time-quantized random sampling scheme is considered to design a nonuniform sampling-based software defined radio (SDR) multistandard receiver. A relaxed design is proposed for an E-GSM/UMTS/IEEE802.11a multistandard receiver. The designed baseband stage avoids the use of the automatic gain control block, relaxes the nonprogrammable antialiasing filter to the third order, and converts data with a 16-bit ADC at a 124-MHz mean sampling frequency.

Pseudorandom clock signal generation for data conversion in a multistandard receiver

In previous work, a non-uniform sampling (NUS) technique to control analog-to-digital conversion (ADC) in a multistandard radio receiver was proposed. In this context of wide band radio signals, the NUS-based ADC offers the advantages of relaxing antialiasing filter (AAF) constraints, decreasing the sampling frequency average and reducing ADC dynamic power consumption. In this paper, we focus on generating non-uniform clock for the sample and hold block of the ADC. The proposed non-uniform clock is based on quantified clock timing. Non-uniform clock is generated from digital control unit (DCU). The DCU is composed of a Gray counter, a linear feedback shift register (LFSR) and a multiplexer to generate specified signals and to select the required clock phase. Simulation results show that performances are similar for conventional uniform sampling (US), additive random sampling (ARS) and time quantized additive random sampling (TQ-RS) for different quantizing factors.

Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters

This paper deals with the problem of clock skew errors in time-interleaved analog-to-digital converters. Deterministic sample-time errors between time-interleaved channels generate nonlinear distortion and degrade SFDR. We propose a fully digital calibration method that uses, on the one hand, adaptive FIR filters to reconstruct a correctly sampled signal and, on the other hand, a new blind clock skew detection algorithm that guides the adaptive filters. This calibration method applies to any number of parallel channels in a time-interleaved architecture. Here, we show theoretical analysis and simulation results for 4 channels case. It is concluded that the calibration technique can greatly attenuate the spurs and improve the SNDR.

An interleaved delta-sigma analog to digital converter with digital correction

Although delta-sigma modulators are widely used for low to moderate rate analog-to-digital conversion, the time over-sampling requirement has limited their application to higher rate converters. This paper presents an architecture wherein multiple delta-sigma modulators are combined with time interlacing. Instead, the system achieves the effect of over-sampling from the multiplicity of delta-sigma modulators. For a system containing M Lth order delta-sigma modulators, approximately L bits of accuracy are gained for every doubling of M. A major benefit of the architecture is that it retains much of robustness of the individual delta-sigma modulators to non-ideal circuit behavior. As a result, the architecture offers the potential of integrating high-precision, high-speed ADC together with digital signal processing functions using VLSI processes optimized for digital circuitry. Because of parallelism, the performance of the architecture is hugely degraded by channel mismatches. A digital technique is used to overcome this problem. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.Keyword spotting (KWS) is an active research issue in recent years. Among existing spotting methods based on pattern matching are DTW method, HMM method and neural network (NN) method, and these method have achieved good result to some certain extent. This paper proposes a new method of keyword spotting based on theory of speech feature space trace time normalization. Experiments show that this method has achieved performance close to that of manual spotting, having some practicability.

A current-mode continuous-time /spl Sigma//spl Delta/ modulator with delayed return-to-zero feedback

In this paper, a design method for continuous-time /spl Sigma//spl Delta/ modulators with RZ feedback pulse is proposed. This method is used to design a second-order continuous-time /spl Sigma//spl Delta/ modulator. The circuit is realized using continuous-time current-mode integrators and switched-current sources DAC. The effect of the integrator thermal noise and nonideal RZ feedback pulse on the system performance is studied. An analog layout language was used to generate the complete layout of the modulator in a 0.6 /spl mu/m CMOS process. With a sampling frequency of 28 MHz, the circuit is expected to achieve 80 dB of dynamic range for a 200 kHz bandwidth input signal. The circuit operates from a power supply of /spl plusmn/1.65 V with a power consumption of 9.1 mW and occupies an area of 0.348 mm/sup 2/.

A 1 V 65 nm CMOS reconfigurable time interleaved high pass ΣΔ ADC

This paper presents a reconfigurable High-Pass (HP) Time-Interleaved (TI) Delta-Sigma (ΣΔ) Analog-to-Digital Converter (ADC) from theoretical and practical points of view. This ADC is designed to fulfill the requirements of GSM, UMTS, WiFi and WiMAX standards. The reconfiguration is performed by adjusting the interpolation factor, the ΣΔ modulator order and the number of active channels thereby allowing bandwidth-resolution trade-off as well as bandwith-power consumption trade-off. The circuit has been fabricated in a 1 V 65 nm CMOS process. Clocked at 50 MHz, the prototype chip consumes 6 mW per channel and the core die area is 2.52 mm2.