Jean-François Naviner

Signal probability for reliability evaluation of logic circuits

Abstract As integrated circuits scale down into nanometer dimensions, a great reduction on the reliability of combinational blocks is expected. This way, the susceptibility of circuits to intermittent and transient faults is becoming a key parameter in the evaluation of logic circuits, and fast and accurate ways of reliability analysis must be developed. This paper presents a reliability analysis methodology based on signal probability, which is of straightforward application and can be easily integrated in the design flow. The proposed methodology computes circuit’s signal reliability as a function of its logical masking capabilities, concerning multiple simultaneous faults occurrence.

Reliability analysis of combinational circuits based on a probabilistic binomial model

Reliability analysis of digital circuits is becoming an important feature in the design process of nanoscale systems. Understanding the relations between circuit structure and its reliability allows the designer to implement some tradeoffs that can improve the resulting design. This work presents a probabilistic model that computes the reliability of combinational logic circuits relating to single and multiple faults. The methodology is targeted (but not limited) to circuits generated by synthesis tools, and standard cell based implementation. To validate the proposed methodology we have studied the reliability of some adder structures. Complexity and scalability of the model are discussed and some optimizations are presented.

Reliability of logic circuits under multiple simultaneous faults

The reliability of integrated circuits has become an unavoidable subject in the nanoscale era. The susceptibility of combinational logic circuits to faults is of increasing interest, and fast and accurate methods are necessary to take the reliability into account earlier in the design process. As circuits scale to nanometer dimensions, the probability of occurrence of multiple simultaneous faults becomes higher and cannot be neglected anymore. In this work, a signal probability reliability analysis (SPRA) algorithm is presented, allowing an evaluation of the reliability of logic circuits relating to multiple simultaneous faults.

Selective hardening methodology for combinational logic

Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context we introduce a cost-aware methodology for selective hardening of combinational logic cells. The methodology is based on the SPRA algorithm for calculating logical masking, and it is capable to automatically perform a trade-off between reliability improvements and associated costs, providing a list of the most effective candidates for hardening. The methodology is applied to a set of benchmark circuits using costs extracted from an actual standard cell library. The results then show that the methodology is able to diminish the unreliability of circuits in a cost-effective manner.

FIFA: A fault-injection–fault-analysis-based tool for reliability assessment at RTL level

Abstract This paper presents an efficient platform for fault robustness estimation of digital circuits. The proposed platform, named FIFA, was designed as a hardware IP to accelerate the Fault Injection and Fault masking Analysis approach. It supports several fault models as well as single and multiple faults. Synthesis results have shown that the proposed platform can exceed those existent in the literature in terms of area efficiency and performance. In addition, the FIFA platform allows the designer to control complexity and completeness of the analysis process.

Reliability analysis of logic circuits based on signal probability

This paper presents a reliability analysis algorithm that can be integrated in the design flow of logic circuits. Based on a four state representation of signal probabilities, and the propagation of this probabilities along the cells of a circuit, the signal reliability of the circuit can be directly obtained. The use of signal probabilities rises the well known problem of signals correlation, and we present some relaxing conditions that allow tradeoffs between accuracy and execution time of the algorithm. The main advantages of the proposed methodology are its simplicity and straightforward application, allowing an easy integration with design tools.

Yield and reliability issues in nanoelectronic technologies

Integrated circuits have known a constant evolution in the last decades, with increases in density and speed that follow the rates predicted in Moore’s law. The tradeoffs in area, speed and power, allowed by theCmos technology, and its capacity to integrate analog, digital and mixed components, are key features to its dissemination in the telecommunications field. In fact, the progress of theCmos technology is an important driver for telecommunications evolution, with the continuous integration of complex functions needed by demanding applications. As integrated circuits evolve, they approach some limits that make further improvements more difficult and even unpredictable. With deep-submicron structures, the yield of manufacturing processes is one of the main challenges of the semiconductor industry, with negative impacts on time-to-market and profitability. With reduced voltages and increased speed and density, the reliability of deep-submicron circuits is another concern for designers, since noise immunity is reduced and thermal noise effects show-up. In this paper we present an overview of the issues related with the scaling of integrated circuits into nanometer technologies, detailing the yield and reliability problems. We present the state of the art in proposed solutions and alternatives that can improve the chances of a large utilization of these nanotechnologies.RésuméLes circuits intégrés ont connu une évolution constante au cours des dernières décennies, avec des améliorations en densité et en vitesse qui suivent les variations prévues par la loi de Moore. Les possibilités offertes par la technologieCmos d’échanges entre surface, vitesse et puissance ainsi que d’intégration de composants analogiques, numériques et mixtes sont la raison principale de la large diffusion de cette technologie dans le domaine des télécommunications. En effet, les progrès de la technologieCmos ont contribué à l’évolution de ce domaine, par l’intégration de fonctions de plus en plus complexes, diverses et demandeuses de puissance de calcul. Néanmoins, plus les circuits intégrés évoluent, plus ceux-ci approchent certaines limites rendant de nouvelles améliorations plus difficiles voire impossibles ou tout au moins imprévisibles. Le rendement des procédés de fabrication employant des structures fortement submicroniques est l’un des défis majeurs de l’industrie des semiconducteurs, du fait de son impact négatif sur le délai de mise sur le marché et la rentabilité. Par ailleurs, la réduction des tensions, l’augmentation des fréquences et l’accroissement de la densité d’intégration font de la fiabilité des circuits fortement submicroniques un autre défi pour les concepteurs, puisque l’immunité au bruit est de ce fait réduite et que les effets du bruit thermique augmentent. Dans cet article, nous établissons un panorama des questions liées à l’arrivée des circuits intégrés en technologies nanométriques en nous intéressant tout particulièrement aux problèmes de rendement et de fiabilité. Nous présentons l’état de l’art des solutions proposées et proposons quelques pistes alternatives qui permettraient de lever les verrous à l’utilisation plus large de ces technologies.

VHDL-AMS behavioral modelling and simulation of high-pass delta-sigma modulator

High-pass /spl Delta//spl Sigma/ modulator has the advantage of immunity from the low frequency noise and is thus very effective in the parallel architectures. In this paper, we present the behavioral modelling and simulation of /spl Delta//spl Sigma/ modulators in VHDL-AMS, and in particular of the high-pass modulator. A set of models in VHDL-AMS suitable for time-domain behavioral simulation of SC /spl Delta//spl Sigma/ modulators is developed. The proposed set of models takes into account at the behavioral level most of SC /spl Delta//spl Sigma/ modulator nonidealities, such as jitter noise, kT/C noise, 1/f noise, amplifier noise, switch nonidealities, amplifier nonidealities, and capacitor mismatch. We elaborate then a top-down design methodology that is validated by the measurement results.

Temporel and spectral analysis of time interleaved high pass sigma delta converter

Delta sigma modulators are widely used for low to moderate rate analog-to-digital conversion. But they are not adapted to high rate conversion because of time oversampling requirement. Parallel architecture is a potential solution to increase the frequency range of /spl Delta//spl Sigma/ ADC, especially the time-interleaved high-pass /spl Delta//spl Sigma/ converter. In this paper, we analyze the immunity from low-frequency offered by the high-pass /spl Delta//spl Sigma/ modulators in time-interleaved /spl Delta//spl Sigma/ ADC. The high-pass /spl Delta//spl Sigma/ modulators not only retains the performance of the converter and eliminates low frequency noise, but also allows simple adaptive channel gain equalization scheme to minimize channel gain mismatch effects by using LMS algorithm.

Reliability aware design of low power continuous-time sigma–delta modulator

Circuit reliability has become a major bottleneck due to ageing degradation. In this paper, reliability-aware methodology and ageing analysis of low power sigma–delta (ΣΔ) modulator are presented. HCI and NBTI are considered as the dominating ageing effects. A second order continuous-time (CT) ΣΔ modulator is implemented for medical application. Ageing estimation is performed at both behavioral and transistor level. Results at behavioral level and transistor level show that the feedback loop in CT ΣΔ modulator is more sensitive and less reliable than the analog loop filter. Comparing with HCI, NBTI is the dominating ageing effect in the designed CT ΣΔ modulator.