Lirida Alves de Barros Naviner

Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction

Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin (~1 nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits.

Multiplexing Sense-Amplifier-Based Magnetic Flip-Flop in a 28-nm FDSOI Technology

A novel low-power nonvolatile magnetic flip-flop is introduced in this paper. The perpendicular magnetic anisotropy spin torque transfer magnetic tunnel junction (STT-MTJ) is used to design the hybrid MTJ/CMOS circuit, which is implemented with 28-nm high-κ metal gate and planar ultrathin body and buried oxide fully depleted silicon on insulator technology. The proposed flip-flop structure named SA-MFF shares a sensing amplifier for normal flip-flop mode and nonvolatile data sensing mode. The modified latch at output stage improves flip-flop latency. The proposed SA-MFF is symmetrical, which provides an equal delay for both true and complementary outputs. It can strengthen weak input signals (minimum 300 mV) and latch them to supply voltage. Forward body biasing transistors allow for fast operation and minimum energy consumption across all modes. The proposed SA-MFF achieves 45.2-ps latency, 50.1-ps clock to output delay, 12.71 μW active power and 343.6 nW of leakage power with 1-V supply voltage, and 6.47-μm × 4.54 μm layout area. Moreover, reliability issues are highlighted with reliability-aware simulations. Process variations of transistors/MTJs and stochastic characteristics of MTJs are investigated. Clock jitter effect and flip-flop metastability are studied.

Compact thermal modeling of spin transfer torque magnetic tunnel junction

Magnetic tunnel junction (MTJ) with spin transfer torque (STT) switching method features fast speed, low power, great scalability and high compatibility with conventional CMOS process. Nevertheless, its magnetic and electrical properties can be easily influenced by operation temperature and self-heating effect, which further results in performance degradation and reliability issues of MTJ based memories and logic circuits. This paper investigates the behaviors of MTJ under different temperatures and further proposes a model in consideration of temperature impact on performance of MTJ, which can be used to optimize the design of STT-MRAM in terms of dynamic operations and temperature tolerance.

Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction

Stochastic Computing (SC) with random bit streams has been used to replace binary radix encoding. SC-based logic circuits take advantage of area minimization, fast and accurate operation and inherent fault tolerance. In this paper, the stochastic characteristics inherent in Spin Torque Transfer Magnetic Tunnel Junction (STT-MTJ) bring on an innovative stochastic number generator (SNM) circuit. The hybrid MOS-MTJ process allows to design a 4T1M structure SNM with 1.98μm*1.46μm layout area, using 28 nm ultra thin body and buried oxide fully depleted silicon-on-insulator (UTBB FD-SOI) technology. A case study of designed SNM is performed by polynomial function synthesis, which significantly reduces area. The proposed circuit also takes advantage of non-volatility and infinite endurance from STT-MTJs, which can be applied to reliability-aware circuits and systems1.

Green solutions for future LTE PMR networks

In this paper we propose different green solutions for adapting the Long Term Evolution (LTE) technology to the Professional Mobile Radio (PMR) requirements. The PMR networks, currently using second generation (2G) technologies, have to evolve to new broadband solutions in order to satisfy their target user demands. The energy consumption is one of the critical points of the broadband solution, and an important constraint for PMR services. We propose different solutions, going from Radio Frequency (RF) level up to the MAC level, for adapting the 4G LTE technology to PMR requirements, reduce the energy consumption and increase autonomy of mobile PMR terminals.

Cross-layer investigation of continuous-time sigma–delta modulator under aging effects

Abstract In order to achieve reliability study in large and complex analog and mixed signal (AMS) circuits and systems, it is required to develop effective reliability-aware design methodologies and exploration tools. This paper discusses two aging mechanisms: hot carrier injection (HCI) and negative bias temperature instability (NBTI) and their effect on 65xa0nm CMOS integrated circuits and systems (ICs). We propose an aging-aware cross-layer approach to comprehensively evaluate aging induced performance degradation at the abstraction (system) level. This approach is composed by hierarchical aging analysis at transistor/circuit level, block failure analysis at abstraction level and system-level aging considerations, which can essentially highlight sensitive blocks for circuit designers. This approach is demonstrated with a continuous-time (CT) sigma–delta ( Σ Δ ) modulator. Analog loop filter and clock distributor are studied with failure boundary and transistor level aging simulation. The aging investigation approach reports system level aging-aware consideration of these building blocks. Results show that amplifiers in analog loop filter have enough margin to cope with aging induced degradations. However, aging risk exists in clock circuits, especially when implementing with high V t transistors. NBTI induced clock jitter from clock distributor can influence clocked block in CT Σ Δ modulator and degrade signal-to-noise ratio (SNR).

Majority voter: Signal probability, reliability and error bound characteristics

The importance of reliability in majority voter is due to its application in both conventional fault-tolerant design and novel nanoelectronic systems. A better understanding of signal probability, functional/signal reliability and error bound of majority voter is discussed in this paper. We analyze these parameters by boolean difference. The equations derived in this paper present the characteristics of error propagations in majority voter, and reveal the conditions that TMR (Triple Module Redundancy) technique requires. The results show the critical importance of error characteristics of majority voter, as used in fault-tolerant designs.

Reliability analysis of a Reed-Solomon decoder

Due to the shrinking of dimension and decreasing of the supply voltage, processors based on deep submicron technologies are more susceptible to defects and errors. This paper presents a model to simulate the behavior of the Reed-Solomon decoder prone to transient faults. The simulation environment developed allows to analyze the influence of the different blocks on the reliability of the decoder. Identifying the most critical blocks of the processor allows the designer to implement a selective hardening strategy and then to minimize the additional costs associated to improve fault tolerance.

Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology

Abstract We investigate stochastic and deterministic reliability problems in the hybrid magnetic tunnel junction (MTJ)/MOS circuit which is implemented with ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FDSOI) technology. A spin torque transfer (STT) magnetic flip-flop (MFF) is designed with ultra wide voltage range, with 0.5xa0V to 1.2xa0V sense/read voltage, and 0.95xa0V to 2xa0V writing voltage, by using an industrial 28xa0nm design kit and a physics-based STT-MTJ compact model. MFF performance can be improved with forward body bias (FBB) technology. The reliability-aware study shows that variability induced read/write failure is more dominant compared with aging induced degradation. Reliability-aware design of STT-MFF is discussed by proper selection of operation voltage.

Approximate computing in MOS/spintronic non-volatile full-adder

Approximate computing and its related topics have shown the potential in next generation computing systems. In this paper, new circuit level design for approximate computing is proposed based on non-volatile (NV) logic-in-memory structure. Two types of NV approximate adders are implemented with circuit reconfiguration and insufficient writing current. Spin torque transfer magnetic tunnel junction (STT-MTJ) is used as NV memory element in magnetic full adder (MFA). The proposed approximate MFAs are implemented with 28nm ultra thin body and buried oxide (UTBB) fully depleted silicon-on-insulator (FD-SOI) technology. Simulation results are presented including power consumption, circuit latency, leakage power, error distance and reliability performance. Low Vdd design strategies are discussed as well.