Runde Zhou

Error Correction Codes and Signal Processing in Flash Memory

This chapter is to introduce NAND flash channel model, error correction codes (ECC) and signal processing techniques in flash memory. There are several kinds of noise sources in flash memory, such as random-telegraph noise, retention process, inter-cell interference, background pattern noise, and read/program disturb, etc. Such noise sources reduce the storage reliability of flash memory significantly. The continuous bit cost reduction of flash memory devices mainly relies on aggressive technology scaling and multi-level per cell technique. These techniques, however, further deteriorate the storage reliability of flash memory. The typical storage reliability requirement is that non-recoverable bit error rate (BER) must be below 10-15. Such stringent BER requirement makes ECC techniques mandatory to guarantee storage reliability. There are specific requirements on ECC scheme in NOR and NAND flash memory. Since NOR flash is usually used as execute in place (XIP) memory where CPU fetches instructions directly from, the primary concern of ECC application in NOR flash is the decoding latency of ECC decoder, while code rate and error-correcting capability is more concerned in NAND flash. As a result, different ECC techniques are required in different types of flash memory. In this chapter, NAND flash channel is introduced first, and then application of ECC is discussed. Signal processing techniques for cancelling cell-to-cell interference in NAND flash are finally presented.

A fully-integrated CMOS UWB transceiver for ultra-low-power short-range application

In short-range UWB communication systems, the low-power design is the most important issue to make UWB technology attractive. A novel trigger receiving algorithm for UWB signals is proposed, which can reduce the system power significantly at the cost of slight performance degrade. A UWB transceiver based on the trigger receiving algorithm is designed and fabricated in HJTC 0.18 µm CMOS process with a total size of 0.45 mm2. The experimental results show that the total power consumption of the transceiver is only 12 mW at 100 Mb/s data rate from a 1.8 V supply, making it suitable for low-power short-range communication. Copyright

A high efficiency CMOS charge pump for low voltage operation

A high efficiency CMOS charge pump suitable for low voltage applications is proposed. To improve the pumping efficiency, the charge pump circuit employs a novel charge transfer switch (CTS) control scheme which combines the backward control scheme with the forward control scheme. In 130nm CMOS process, the simulation results have shown that the proposed charge pump has higher pumping efficiency compared to other charge pumps1.

Embedded high-speed BCH decoder for new-generation NOR flash memories

A high-speed double-error-correcting (DEC) BCH decoder for new-generation NOR flash memory is presented to improve reliability. To speed up the decoding process, a multiplication-free linear transform is developed to eliminate iterations and divisions in Galois fields. Furthermore, a reverse data-flow analysis (RDFA) and smoothest descent approach are proposed to reduce latency in the bit-parallel Chien search. Based on peripheral 180nm CMOS process, the whole BCH decoder is designed and the latency is significantly reduced to less than 5ns.

An MBOK-UWB SoC transceiver in 0.181μm CMOS technology

A system-on-a-chip (SoC) pulse-based MBOK-UWB transceiver for high-speed wireless transmission is presented in this paper. The system achieves the data rate of 100 Mbps. The digital baseband implements RAKE receiving architecture, with M-ary bi-orthogonal keying (MB OK) spread spectrum modulation, low-density parity-check (LDPC) error-correct coding and Ethernet interface. The front-end circuits include low-power pulse generator, 3~5GHz wideband low-noise amplifier (LNA) and 1 Gsps 4 bit flash analog-to-digital converter (ADC). These modules of proposed SoC has been designed and fabricated in HJTC 0.18 mum 1P6M CMOS technology. The baseband had been designed and implemented in one Xilinx FPGA.

An on-chip high-speed 4-bit BCH decoder in MLC NOR flash memories

An on-chip high-speed 4-bit BCH decoder for error correcting in a MLC NOR flash memory is presented. As process shrinking beyond 45nm, double-error-correcting (DEC) BCH code is needed for reliability requirement. A novel fastdecoding algorithm is developed by eliminating finite field divisions and combining arithmetic operations. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of the 4-bit BCH decoder in a 2b/cell NOR flash memory is proposed to obtain a good time-area trade-off. Simulation results show that the latency of the 4-bit BCH decoder achieves only 6.4ns and satisfies fast access time of a NOR Flash memory.

A fully integrated CMOS UWB transmitter

In this paper, a fully integrated CMOS UWB transmitter is presented. The presented UWB transmitter consists of a low voltage differential signal (LVDS) receiver to be driven with high data rate input, a pulse generator to produce sub-nanosecond Gauss-like pulses at each rising edge of input data and a driver amplifier to shape the pulses and to drive 50-ohm antennas. Fabricated in an HJTCs 0.18mum mixed signal CMOS technology, the transmitter can generate 500ps width pulses at a repetition rate of over 500Mpps and consumes less than 4mW. The presented transmitter has a small core size of around 100 mum times 150 mum.

a new type of high-performance low-power low clock-swing TSPC flip-flop

A new type of pulse-triggered true single phase clock (TSPC) flip-flop with low threshold voltage clock transistor and its several improved structures are proposed for high-performance low-power applications. Due to low clock-swing and double-edge triggering, the power consumption of the clock network is estimated to reduce by 78%. HSPICE simulation with 0.18 mum CMOS technology shows that their delay, power dissipation and PDP are reduced by 20~44%, 40~56% and 61~72% respectively, when compared with the existing Low-Swing Clock Double-Edge Triggered Flip-Flop (LSDFF).

Low power inductor-less pulse UWB transceiver

This paper presents a new trigger receiving algorithm of the pulse UWB signal, aimed at eliminating the high requirement of process variation as well as the dependence on ultra-high sampling rate and circuit operating speed in conventional correlation receiving algorithm. This algorithm can reduce both circuit complexity and power consumption largely. Based on the proposed receiving algorithm, a fully integrated low power inductor-less pulse UWB transceiver is designed and fabricated in HJTC 0.18µm CMOS process with a total size of 0.45 mm2. The experimental results show that the total power consumption of the transceiver is only 7.2mW at 42Mb/s data rate from a 1.8V supply.

Design of a fully pipelined single-precision floating-point unit

A fully pipelined single-precision floating-point unit is proposed in this paper. It is implemented in three pipeline stages. The core of this design is a multiply-add-fused unit. With the assistance of a lookup table and the control logic, it also implements floating-point division and square root operations, besides the basic addition, subtraction and multiply-add-fused operations. It is modeled in VerilogHDL and synthesized in 0.18 mum CMOS technology after verification. Experiment result shows that there is only 3% time penalty compared with the traditional multiply-add-fused unit.