Luc Guerin

Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10 000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nF/mm2 is achieved with two-layer Si interposer chip stacks.

C4NP Technology for Lead Free Solder Bumping

C4NP is a novel solder bumping technology developed by IBM that addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping using a variety of lead-free solder alloys. It is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass molds. The glass mold contains etched cavities which mirror the bump pattern on the wafer. Filled mold and wafer are brought into close proximity/soft contact at reflow temperature and solder bumps are transferred onto the entire 300 mm (or smaller) wafer in a single process step without the complexities associated with liquid flux. The simplicity of the process makes it a low cost, high yield and fast cycle time solution for bumping with a variety of high performance lead free alloys. The focus of this paper is on the mold fabrication, solder fill and inspection steps prior to solder transfer including high volume manufacturing tool designs. Yield improvements from the mold suppliers and mold specs are discussed. Finally, the results from a detailed cost model are reviewed. This cost model includes a comparison of C4NP versus alternative bumping techniques and includes capital, materials, and labor cost factors. The data in this paper are provided by the IBM Systems and Technology Group in the Hudson Valley Research Park, NY.

Bonding technologies for chip level and wafer level 3D integration

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm2. Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

Reliable through silicon vias for 3D silicon applications

The use of through silicon vias (TSVs) is required to implement 3D chip stacking technology. This work explores a method to fabricate highly reliable TSVs that is compatible with CMOS processing. The key feature of the TSVs is a redundant tungsten bar with a high temperature thermal oxide insulating liner. Care must be taken when exposing the TSVs from the back side so that material is not left on the surface that can cause a leakage path to the silicon wafer. TSVs were produced with that had no fails through standard JDEC testing.

End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications

The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level “device” side copper wiring, with line space (L/S) of ≤ 2.5 μm, built using damascene techniques, a 55 μm glass core with through glass vias (TGVs), and multiple UBM levels finished with tin silver (SnAg) C4 bumps. The 300mm TGV wafers are processed on existing silicon wafer manufacturing equipment following established, integrated silicon process flows. Once fully processed, the glass wafers are diced, and the interposer joined to a ceramic carrier by mass reflow. Sub-assemblies are then underfilled, the top die attached, and lidding completed. The final assemblies are tested to evaluate performance of chip to chip interconnects, chip-to-package (through interposer) interconnects, and chip-to-PCB (through interposer and package) interconnects. Results of loss vs frequency measurements are compared, for the glass interposer against the existing silicon interposer results.

Stress reduction methods within the Far Back End of Line (FBEOL) for fine pitch and 2.5D/3D packaging configurations

Fine pitch interconnects combined with 2.5D/3D packaging technology offers enormous potential towards decreasing signal latency and by making it possible to package increased electrical functionality within a given area. However, fine pitch interconnects present their own set of challenges not seen in packages with coarse pitch interconnects. Increased stresses within the Far Back End of Line (FBEOL) and Back End of Line (BEOL) layers within the chip are the primary concerns. Several 2D and 2.5D test vehicles with fine pitch and coarse pitch interconnects were built and tested for mechanical integrity by subjecting them to accelerated thermal cycling between -55°C and 125°C. Finite-element based mechanical modeling was done to determine the stress level within the FBEOL layers of these test vehicles. For all the tested assemblies, experimental data and modeling results showed a strong correlation between reduced pitch and increased level of stresses and increased incidence of failures within the FBEOL region. These failures were observed exclusively at the passivation layer and aluminum pad inter face. Experimental data in conjunction with mechanical modeling was used to determine a safe level of stress at the aluminum interface. Global and local design changes were explored to determine their effect on the stresses at this interface. Several guidelines have been provided to reduce these stresses for a 2.5D/3D package assembly with fine pitch interconnects. Finally, an optimized configuration has been proposed that is expected to be robust with very low chance of failure within the FBEOL region.