Jean Audet

Design optimization for isolation in high wiring density packages with high speed SerDes links

This paper discusses design tradeoffs for high speed signal performance in buildup laminate packages with high wiring density. Trace design in die escaping area, PTH vias placement pattern and BGA I/O assignments are analyzed in depth for design optimization through numerous simulations as major areas of high coupling concern and channel performance. Then design suggestions are made at each area for performance and cost optimization and design strategies are developed to achieve the overall required performance as a whole system. Lastly some coupling test results on HSS links are presented to verify the performance of the design

Electrical design and performance of a multichip module on a silicon interposer

A multichip module package has been designed in IBMs silicon technology. The module consists of two chips of same size and type communicating horizontally through a silicon interposer to a large ASIC chip. The chip to chip links operate at 8 Gbps with a loss of 0.5 dB/mm and reflections <; 20 dB. All links are skew matched to within 2 ps. Model to hardware correlation was performed and trace loss is within 0.1 dB of modeling data. The input to the module consists of a high speed RF signal and the module was optimized for board to package transition. Outputs of the module are 15Gbps high speed links. Both input and output signals go up or down a through silicon via (TSV) in the silicon interposer as part of their electrical paths. TSV parameters do not limit the electrical performance of the module.

Development of a Low CTE chip scale package

This paper describes the development of a low CTE organic Chip Scale Package (CSP) jointly by KST and IBM. Tests carried out on the low CTE laminate material and subsequently on the related CSP are described. The new material set, identified as Advanced SLC Package, combines low CTE core and build-up dielectric materials to achieve a composite laminate CTE of 9-12 ppm/°C, which is intermediate between the CTEs of silicon device and conventional board. The lower composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI) and white bumps. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. Global and chip-site warp data from thermo-mechanical modeling are compared to the measured warp data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated.

Effect of organic package core via pitch reduction on power distribution performance

Advances in CMOS technology continue to provide increased circuit density and performance at a lower cost. Die size and cost can be further reduced for I/O limited applications by shrinking the area array flip-chip (C4) pad pitch. These advances continue to drive package ground rule improvements to efficiently distribute signal and power while reducing cost. One such groundrule for organic build-up packages is the core via pitch. Core via pitch reduction can significantly improve the package power distribution and signal escape. This paper presents the package design tradeoffs for core via pitch reduction to support a 90nm 9.3mm ASIC die using a 150/spl mu/m full area array C4 pitch. The impact of core via pitch on power distribution performance, wireability, and cost will be presented, including electrical modeling and simulation results. Design trade-offs to optimize both the chip and package are presented, including die C4 pad pitch and depth versus module cost and performance.

Comparison of multilayer organic and ceramic package simultaneous switching noise measurements using a 0.16 /spl mu/m CMOS test chip

This paper presents a comparison of simultaneous switching-output noise measurements taken with a 0.16 /spl mu/m CMOS test chip on two flip-chip multilayer packages: IBMs new HyperBGA/sup TM/ high-density PTFE-based organic BGA, and an existing IBM ASIC-menu alumina-ceramic BGA. In two classes of tests, measured transmitted noise from the organic BGA was found to average less than half that of the ceramic BGA. Technology and design features of the chip and package test vehicles are described and compared. Several types of simulations, including extracted loop inductance and full-wave simulation of coupling parameters, identify various noise components in each package and elucidate the large differences in measured noise between the two packages.

Electrical modeling and characterization of packaging solutions utilizing lead-free second level interconnects

This paper presents measured and modeled results of two novel lead-free interconnect solutions. A surface mounted Copper Column Grid Array (CuCGA) and a demountable Spring Land Grid Array (SLGA) will be characterized and compared to the standard Column Grid Array (CGA). The geometries and materials required for reliable connections often compete with the ones required for adequate electrical performance. To characterize the electrical performance differences, several IBM ASIC menu alumina packages were built, vatying the physical propelties of the second level interconnects for both the CuCGA and SLGA technologies. The corresponding parts were modeled and measured for loop inductance and DC resistance of the power distribution system. Excellent model to hardware correlation was achieved, and clear candidates are recommended for equivalent or better performance compared to standard CGA interconnects.

Advanced laminate carrier module warpage considerations for 32nm pb-free, FC PBGA package design and assembly

The trend in large body, high performance integrated circuit packaging for the 32 nm semiconductor node and beyond is towards low dielectric loss to enable high bandwidth / low loss channels, and low thermal expansion to protect fragile, ultra-low dielectric constant (k) chip dielectric materials from differential expansion stress. A low coefficient of thermal expansion (CTE), low dielectric loss laminate composite was developed using industry standard Sequential Build Up (SBU) fabrication techniques and novel laminate materials. This laminate technology was used in assembly of a Flip Chip Plastic Ball Grid Array (FC PBGA) module including a silicon test structure developed for 32 nm Custom Logic development. The same silicon test structure and laminate design were also used to fabricate modules using conventional high volume laminate materials. Various laminate physical parameters including composite CTE were determined. The warpage shape of each laminate was initially characterized at room temperature, and over the temperature range from 25°C to 240°C. Warpage of critical package features was measured and tracked throughout the various steps of the lead free flip chip module assembly process for multiple laminate cross sections, core and buildup materials. A quantity of assemblies of each type was built and measured, data is reported. Advantages and disadvantages of each laminate module type and implications for robust package assembly as evidenced by these results are discussed.

Comparison of simultaneous switching noise measurements using netlist compatible multilayer ceramic packages having variously compromised reference planes

This paper presents a comparison of simultaneous switching-output noise and skew measurements taken with a 0.12 /spl mu/m CMOS test chip on three flip-chip, multilayer-ceramic, single-chip modules (SCMs) having differing amounts of reference mesh and power-supply vias in the package under the chip outline. Missing reference mesh equates to poor current-return paths for signals traversing such package regions. Missing power-supply vias equate to increased supply inductance. The test chip has 732 individually programmable off-chip output buffers, each of which can be individually probed. The first package has full reference mesh under the chip. The second package has reference mesh only in the upper half of the package under the chip. The third package has essentially no reference mesh under the chip. Technology and design features of the chip and package test vehicles are described. Noise and delay measurement techniques and results are presented. The large number of off-chip output buffers enables a statistical view of transmitted noise and skew behavior as signal current-return paths are compromised. This analysis is graphically presented and discussed. Several types of simulations, including extracted loop inductance and full-wave simulation of coupling parameters, are presented. These simulations elucidate the large differences in measured transmitted noise and off-chip output buffer skew between the three packages.

ASIC packaging challenges with high speed interfaces

Networking speed is exploding as demanded with technology advancements and industry chip technology is evolving with rapidly increasing serial link data rates with high link integration for higher aggregate bandwidth and shrinking chip area and interface dimensions of devices. However, a large development speed gap between chip technologies and package technologies places great packaging challenges for high speed link applications where package wireability is driven by high frequency performance requirements. This paper discusses packaging challenges of high speed link applications with cost-performance tradeoffs in the technology trend.

End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications

The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level “device” side copper wiring, with line space (L/S) of ≤ 2.5 μm, built using damascene techniques, a 55 μm glass core with through glass vias (TGVs), and multiple UBM levels finished with tin silver (SnAg) C4 bumps. The 300mm TGV wafers are processed on existing silicon wafer manufacturing equipment following established, integrated silicon process flows. Once fully processed, the glass wafers are diced, and the interposer joined to a ceramic carrier by mass reflow. Sub-assemblies are then underfilled, the top die attached, and lidding completed. The final assemblies are tested to evaluate performance of chip to chip interconnects, chip-to-package (through interposer) interconnects, and chip-to-PCB (through interposer and package) interconnects. Results of loss vs frequency measurements are compared, for the glass interposer against the existing silicon interposer results.