Daniel George Berger

3D copper TSV integration, testing and reliability

Node-agnostic Cu TSVs integrated with high-K/metal gate and embedded DRAM were used in functional 3D modules. Thermal cycling and stress results show no degradation of TSV or BEOL structures, and device and functional data indicate that there is no significant impact from TSV processing and/or proximity.

Three-Dimensional Chip Stack With Integrated Decoupling Capacitors and Thru-Si Via Interconnects

In this letter, the integration of CMOS-compatible thru-Si via (TSV) interconnects with deep-trench decoupling capacitors is demonstrated. Reliability test is performed with a 65-nm CMOS test chip on top of a 3-D Si interposer chip that contains 10 000 TSV interconnects. Multilayer stacking is also demonstrated, and capacitance density of 280 nF/mm2 is achieved with two-layer Si interposer chip stacks.

An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates

In this work, a controlled thermo-compression (TC) bonding process has been developed to address problems caused by interposer and laminate warpage when assembling large three-dimensional (3D) integrated circuit (IC) die on an organic substrate (laminate). By using TC bonding, a thin interposer with through-silicon-vias (TSV) is joined to a top die while being held flat by vacuum and vertical pressure. A vacuum distribution plate is developed and used to mitigate warpage during 3D assembly. A unique set of process parameters has been developed which enables the joining of severely bowed, large area interposers to a semiconductor die without C4 (Controlled Collapse Chip Connection) shorting. The controlled TC bonding method developed in this work offers a huge advantage when joining multiple large warped die in a stack. This evaluation used a large 22 nm CMOS top die with ultra low-K (ULK) back end of the line (BEOL) and copper pillar/SnAg solder bumps at two different pitch sizes, 61 μm and 131 μm. Both the top die and interposer die were larger than 600 mm2 while the organic substrate was 68.5 mm × 68.5 mm. The top die and interposer were bonded with parameters developed for an enhanced TC bonding process. Cross-sectional analysis of the 3D assembly showed that the solder joints along the perimeter of chips exhibited good joining with good solder wettability and no solder bridging. Non-destructive X-ray analysis also confirmed that there were no C4 bump bridging across the entire chip area. The experimental results verified that the enhanced TC bonding process can effectively prevent C4 bump bridging and C4 bump electrical opens for a large die packaged in a 3D configuration with a highly warped large area silicon interposer.

Dual-Level Metal (DLM) method for fabricating thin film wiring structures

This paper describes a fabrication method for multilevel, thin film wiring in which each wiring level and a solid via or stud to the level below, are formed as one integral unit. The processing scheme described makes use of a photosensitive polyimide (PSPI) for defining the wiring channels and a non-photosensitive polyimide for the vias. The via opening in the non-photosensitive polyimide is formed by laser ablation while the wiring channels are formed in the PSPI layer by photolithography. The via hole and the channels in the PSPI are filled in the same metallization step consisting of electroplating copper over a sputtered seed layer. The wiring pattern is finally delineated when a planarization step removes the excess plated copper. This processing method, which we refer to as the Dual Layer Metallization (DLM) method, is found to be very economical, in terms of the number of process steps involved, for forming multilevel, polyimide-copper wiring structures.<<ETX>>

Bonding technologies for chip level and wafer level 3D integration

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm2. Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

Electrical design and performance of a multichip module on a silicon interposer

A multichip module package has been designed in IBMs silicon technology. The module consists of two chips of same size and type communicating horizontally through a silicon interposer to a large ASIC chip. The chip to chip links operate at 8 Gbps with a loss of 0.5 dB/mm and reflections <; 20 dB. All links are skew matched to within 2 ps. Model to hardware correlation was performed and trace loss is within 0.1 dB of modeling data. The input to the module consists of a high speed RF signal and the module was optimized for board to package transition. Outputs of the module are 15Gbps high speed links. Both input and output signals go up or down a through silicon via (TSV) in the silicon interposer as part of their electrical paths. TSV parameters do not limit the electrical performance of the module.

Prototype of multi-stacked memory wafers using low-temperature oxide bonding and ultra-fine-dimension copper through-silicon via interconnects

Reported for the first time is proof-of-concept multi-stacking of memory wafers based on low-temperature oxide wafer bonding using novel design and integration of two types of ultra-fine-dimension copper TSV interconnects. The combined via-middle (intra-via) and via-last (inter-via) strategy allows for the greatest degree of interconnectivity with the tightest allowable pitches and permits a highly integrated interconnect system across the stack. In combination with the successful metallization of the ultra-fine-dimension TSVs, the present work has shown the viability to extend the perceived TSV technology beyond the ITRS roadmap.

Reliable through silicon vias for 3D silicon applications

The use of through silicon vias (TSVs) is required to implement 3D chip stacking technology. This work explores a method to fabricate highly reliable TSVs that is compatible with CMOS processing. The key feature of the TSVs is a redundant tungsten bar with a high temperature thermal oxide insulating liner. Care must be taken when exposing the TSVs from the back side so that material is not left on the surface that can cause a leakage path to the silicon wafer. TSVs were produced with that had no fails through standard JDEC testing.

Impact of 3D copper TSV integration on 32SOI FEOL and BEOL reliability

We integrated a copper TSV (Through Silicon Via) cell in a qualified 32SOI CMOS logic technology with high-K/metal gate and DT (Deep Trench) capacitors. Extensive wafer level characterization and reliability stressing were performed to evaluate the impact of the TSVs and 3D (3-Dimensional) integration processing on device and back end of line reliability performance. This included bias temperature instability stress, hot carrier injection, thermal cycling, wiring electromigration testing, and time-dependent dielectric breakdown studies. The integration of the TSV and process shows an equivalent reliability performance with respect to the 2D baseline for FEOL (Front End of Line) and BEOL (Back End of Line) structures within the assigned 3D design rules. In particular it is demonstrated that this TSV design allows BEOL structures at zero proximity to the KOZ (Keep Out Zone). Further, device and functional data indicate that there is no change in end of life reliability targets from TSV processing and/or proximity.

End-to-End Integration of a Multi-die Glass Interposer for System Scaling Applications

The processes key to enabling 3D manufacturing, namely, bond, backgrind, and through silicon via (TSV) reveal, are extended for 300 mm glass substrates to fabricate a heterogeneous, multi-die, 2.5D glass interposer. Based on an existing silicon interposer offering, the glass interposer is comprised of multi-level “device” side copper wiring, with line space (L/S) of ≤ 2.5 μm, built using damascene techniques, a 55 μm glass core with through glass vias (TGVs), and multiple UBM levels finished with tin silver (SnAg) C4 bumps. The 300mm TGV wafers are processed on existing silicon wafer manufacturing equipment following established, integrated silicon process flows. Once fully processed, the glass wafers are diced, and the interposer joined to a ceramic carrier by mass reflow. Sub-assemblies are then underfilled, the top die attached, and lidding completed. The final assemblies are tested to evaluate performance of chip to chip interconnects, chip-to-package (through interposer) interconnects, and chip-to-PCB (through interposer and package) interconnects. Results of loss vs frequency measurements are compared, for the glass interposer against the existing silicon interposer results.