Luca Perugini

Input/Output Pad for Direct Contact and Contactless Testing

Non-contact probing can provide an important contribution for testing complex Systems-on-a-Chip (SoC), Systems-in-a-Package (SiP) and Through-Silicon-Vias (TSV) interconnections. This paper demonstrates the feasibility of wireless testing by capacitive coupling between a cantilever probe card and a pad. In particular a scheme of an I/O pad suitable for both contact and contactless probing is proposed.

Chip-to-chip communication based on capacitive coupling

This paper presents a review of the solutions proposed for chip-to-chip communication based on capacitive coupling. Circuit designs, assembly options and various different test cases are presented in this work. It is shown that this 3D technology is capable of transferring digital data between two dies at high-speed with low power consumption, and likewise analog signals without the need for any extra-wafer processing. The results presented highlight the key features of capacitive coupling when compared to other 3D interconnections and justify the effort to overcome some open issues and make it a marketable technology.

System on chip with 1.12mW-32Gb/s AC-coupled 3D memory interface

An AC-coupled 3D memory interface for chip-to-chip communication is implemented in 90nm CMOS technology. It transfers 128 bit words between stacked SRAMs in an ARM-based System on Chip (SoC) platform at 250MHz. This interface requires 0.05mm2 of occupation area and achieves a 32Gbit/sec of throughput and an average energy consumption of 35µW/Gbit/sec.

Multicore Signal Processing Platform With Heterogeneous Configurable Hardware Accelerators

The computing demand of many signal processing algorithms is dramatically growing because of the increasing complexity of embedded software applications. Concurrently, as process technology scales, the design effort for realizing very large scale integrated circuits and the associated costs are becoming critically high. A possible solution to address this performance/costs challenge is given by customizable multiprocessor system-on-chips. The approach proposed in this paper leads to the customization of multi/many processor system-on-chip at two levels of abstraction: 1) customization through application-specific hardware accelerators implemented on configurable datapath that can target three kinds of structured application-specific integrated circuit technologies: metal, via, and runtime programmable and 2) customization of the architectural parameters of the platform. The proposed platform is equipped with a design framework that assists the user in the high-level design-space exploration of signal processing applications described using the Open Computing Language (OpenCL) language. A peculiar added value of the flow is to support the migration of OpenCL kernels and tasks into pipelined hardware accelerators described using a C-level language. The platform is able to provide an average performance of 90 GOPS on a set of reference signal processing applications, and an average computational energy efficiency of 130 GOPS/W in its metal-programmable configuration. This result shows the benefits in terms of energy efficiency of hardware customization applied to multiprocessor systems with respect to many core devices such as general-purpose graphic processing units, able to provide on average 2.5 GOPS/W for the applications under analysis.

3D system on chip memory interface based on modeled capacitive coupling interconnections

A memory interface for a 3D System-on-a-Chip based on capacitive coupling is implemented in 90nm CMOS technology. The design choices have been driven by an innovative 3D extraction and simulation flow. The presented work exploits AC capacitive coupling for chip-to-chip communication running up to 250MHz. The interface transfers 128 bit words between stacked SRAMs in an ARM-based System-on-a-Chip (SoC). The 3D memory interface achieves a total throughput of 32Gbit/sec with an average energy consumption of 35μW/Gbit/sec and an area occupancy of 0.05mm2.

A 40 nm CMOS I/O Pad Design With Embedded Capacitive Coupling Receiver for Non-Contact Wafer Probe Test

A receiver for capacitive coupled communication is embedded in a digital input/output pad to add the capacity for non-contact data communication, while maintaining size, ESD protection, and buffering functions unchanged, even in contact mode. The added feature allows non-contact probing of die pads and provides a reliable alternative solution to mechanical probing for electrical wafer sort testing of Systems-on-Chip (SoC) and Systems-in-Package (SiPs) because of elimination of pad damage and reduction of the force required to create stable electrical contacts between probe needles and pads. The proposed receiver detects the displacement current flowing through the capacitive channel created between the connecting probe needle and top metal pad surface when a transition in the input digital stimulus signal occurs. The receiver is designed to work up to 100 Mbit/s data rate with a power of 340 μW in a 40 nm CMOS process. The circuit trade-offs between frequency, amplitude of the step input and distance are discussed. Experimental results show that for a 5 V input voltage amplitude, the receiver allows correct data transmission at a distance up to 5 μm, which increases to 10 μm if the top aluminum layer is divided in two, using a customized I/O pad design. The feasibility of this non-contact testing approach was verified through electrical tests on two IP blocks, an LFSR, and a PLL with a scan chain, using a standard prober and a cantilever probe card designed with 19 needles of different lengths to enable both physical contact connections for power supply and non-contact capacitive coupling data communication for signals.