Roberto Canegallo

A textile based capacitive pressure sensor

This paper introduces an approach for decoding the pressure information exerted over a broad piece of fabric by means of capacitive sensing. The proposed sensor includes a distributed passive array of capacitors (i.e. an array where no active elements are involved), whose capacitance depends on the pressure exerted on the textile surface, and an electronic system that acquire and process the subsequent capacitance variations. Capacitors can be made in different ways, though, in our demonstrator they have been implemented between rows and columns of conductive fibers patterned on the two opposite sides of an elastic synthetic foam. Measures performed over a prototype has been demonstrated the reliability of the approach by detecting pressure images at 3 F/s and by measuring capacitances as low as hundreds of fF spaced apart at meters of distance.

3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly

This paper presents a 3D interconnection scheme based on capacitive coupling. We propose synchronous communication circuits, based on a precharge and transmission approach, that provide an optimization of interconnection sensitivity. Measurements on a 0.13 ¿m CMOS implementation demonstrate working connections with an area occupation of 8 × 8 ¿m2 . Experimental results are presented for both die-to-die and wafer-to-wafer assembly techniques. They show a maximum communication bandwidth of 1.23 Gb/s, leading to a throughput per area of 19 Mb/s/¿M2 with an energy consumption of 0.14 mW/Gb/s. BER measurements demonstrate the reliability of these AC interconnections with no error on more than transmitted.

3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities

A wireless interconnection scheme based on capacitive coupling provides mono- and bi-directional transmission capabilities for 3-D system integration. Chips are implemented in 0.13 mum CMOS technology and assembled face-to-face at die-level. RX-TX circuits are specifically designed for low-power functionality and the implementation takes advantage of the two different voltage thresholds that are available for the standard transistors in the CMOS process we used. The communication circuits are coupled via electrodes with an area down to 8 times 8 mum2 and this enables the vertical propagation of clock signals at 1.7 GHz, a propagation delay of 420 ps for general purpose signals and a throughput of more than 22 Mb/s/mum2 with 0.08 pJ/b energy consumption.

A dynamically reconfigurable monolithic CMOS pressure sensor for smart fabric

This paper presents a mixed-signal system-on-chip (SOC) for sensing capacitance variations, enabling the creation of pressure-sensitive fabric. The chip is designed to sit in the corner of a smart fabric such as elastic foam overlaid with a matrix of conductive threads. When pressure is applied to the matrix, an image is created from measuring the differences in capacitance among the rows and columns of fibers patterned on the two opposite sides of the elastic substrate. The SOC approach provides the flexibility to accommodate for different fabric sizes and to perform image enhancement and on-chip data processing. The chip has been designed in a 0.35-/spl mu/m five-metal one-poly CMOS process working up to 40 MHz at 3.3 V of power supply, in a fully reconfigurable arrangement of 128 I/O lines. The core area is 32 mm/sup 2/.

On a road tire deformation measurement system using a capacitive–resistive sensor

This paper presents a novel approach to continuously measure the mechanical deformations of a tire due to contact with asphalt, by embedding capacitive–resistive sensors in it. A strain monitoring method is proposed, which adopts the tire itself as a sensing element. In this way, the sensing area is pushed towards the tread interface (the part of the tire in direct contact with the asphalt), where the information concerning tire state is actually generated. Tire deformation causes a change of the spacing between the steel wires inside the tire carcass and this change is translated into an impedance change of that region of the tire. By measuring such an impedance change, our approach makes it possible to determine the deformation of the tire. Static stress–strain measurements show a linearity of about 80% in the impedance–strain relation. A linear impulse of tensile strain has been used to validate the detection of instantaneous changes in the tread–asphalt interface. The mechanical solicitation resulted in a 1% deformation of the specimens main dimension. Experimental results report a change of about 40% in the real part of the impedance and a change of about 20% in the imaginary part of the impedance. The same measurements have been performed varying the temperature within a range of −20 to 90 °C, which is compatible with the operating conditions of a commercial car tire.

A 0.14mW/Gbps high-density capacitive interface for 3D system integration

This paper presents a synchronous 3D interconnection based on capacitive coupling. The designed link presents a power consumption of 0.128mW/pin@975Mbps/pin, overcoming standard I/O pads performance of two orders of magnitude. High bit-rate, reduced power consumption and electrode area down to 8/spl times/8/spl mu/m/sup 2/ enable the implementation of highly parallel pipelined interfaces for inter-chip communication, with an aggregate consumption of about 0.14mW/Gbps.

1 M-cell 6b/cell analog flash memory for digital storage

This standard flash-EEPROM contains 1 M cells with multi-level programming of up to 64 digital levels per cell, providing a prototype of a 6 Mb memory with 257 Mb/cm/sup 2/ array density.

Flash-based programmable nonlinear capacitor for switched-capacitor implementations of neural networks

The use of flash devices for both analog storage and analog computation can result in highly efficient switched-capacitor implementations of neural networks. The standard flash device suffers from severe limitations in this application due to relatively large parasitic overlap capacitances. This paper introduces the computational concept, circuit and architecture we are exploring as well as a novel flash-based programmable nonlinear capacitor with much improved charge domain characteristics for our application. These devices are demonstrated in a novel circuit consisting of only two devices and capable of computing a 5-bit absolute-value-of-difference at an energy consumption of less than 1 pJ.<<ETX>>

Low leakage circuit design for FPGAs

Reconfigurable computing is well suited for wireless applications because of its capability to adapt to changing communication protocols. However, as technology scales, FPGAs could suffer from leakage energy consumption due to the large number of inactive transistors. This paper presents different buffered switches mixing low and high threshold transistors which trade some delay performance to reduce by two orders of magnitude the leakage current of the switch blocks which generate most of the dissipation in FPGAs.

A reconfigurable processor architecture and software development environment for embedded systems

Flexibility, high computing power and low energy consumption are strong guidelines when designing new generation embedded processors. Traditional architectures are no longer suitable to provide a good compromise among these contradictory implementation requirements. In this paper we present a new reconfigurable processor that tightly couples a VLIW architecture with a configurable unit implementing an additional configurable pipeline. A software development environment is also introduced providing a user-friendly tool for application development and performance simulation. Finally, we show that the HW/SW reconfigurable platform proposed achieves dramatic improvement in both speed and energy consumption on signal processing computation kernels.