Lucas Brusamarello

Statistical RTS model for digital circuits.

Abstract In this work we study the variation in drain current of MOS transistors due to the capture and emission of electrons at interface states (traps), called random telegraph signal (RTS). Usually, RTS is studied in frequency domain. However, for digital circuits, it is more appropriate to use time-domain representations. The time-domain representation here proposed models the effect of RTS on I ds as instantaneous Vt shifts. We introduce a statistical numerical approach for computing the total Δ Vt of the transistor considering all the traps in the interface. The method analyses the effect of non-uniform charge densities along the channel. To show the applicability of the methodology to circuit analysis on the electrical level, the model is applied to characterize read and write instability failures caused by RTS on a 6T-SRAM cell.

Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants

A new methodology for circuit level transient simulation of Random Telegraph Noise (RTN) is proposed. The physically based methodology properly models the microscopic phenomena involved in RTN, including their stochastic nature. Using a modified BSIM code, the compact model is implemented in a SPICE simulator, accounting for non-stationary RTN effects under arbitrary bias. The probability of traps to capture or emit charge carriers is updated at each time step of the transient simulation according to the actual bias conditions of the device. Atomistic device simulations are performed in order to study the impact of trap position along the channel on the amplitude of the contribution of a trap to RTN. These device simulations take into account short-range Coulomb interactions and show the relevance of large local deviations of mobility values of carrier electrons, particularly for traps near the source end of the channel. As a case study, jitter in an oscillator is simulated. It is shown that the methodology properly addresses open issues in the literature, by properly accounting for bias-dependent, non-stationary statistic of RTN phenomena relevant to the design of integrated circuits.

A NOVEL AND PRECISE TIME DOMAIN DESCRIPTION OF MOSFET LOW FREQUENCY NOISE DUE TO RANDOM TELEGRAPH SIGNALS

Nowadays, random telegraph signals play an important role in integrated circuit performance variability, leading for instance to failures in memory circuits. This problem is related to the successive captures and emissions of electrons at the many traps stochastically distributed at the silicon–oxide (Si–Si O2) interface of MOS transistors. In this paper, we propose a novel analytical and numerical approach to statistically describe the fluctuations of current due to random telegraph signal in time domain. Our results include two distinct situations: when the carrier trap energy state density at the interface is uniform, and when it is an u-shape curve as prescribed in literature, described here as simple quadratic function. We establish formulas for relative error as function of the parameters related to capture and emission probabilities. For a complete analysis, experimental u-shape curves are used and compared with the theoretical aproach.

NBTI-aware technique for transistor sizing of high-performance CMOS gates

NBTI imposes a challenge for the design of circuits in DSM technologies. NBTI causes increase of Vt of the PMOS transistors, thus leading to timing degradation of CMOS circuits over time. This manuscript presents a NBTI-aware transistor sizing technique for high-performance CMOS gates, which improves the cell reliability with minimum area penalty. The delay of an inverter designed on a 32nm technology using our methodology presents 6% delay reduction at year 3 compared to a traditional sizing methodology, both using the same area. For a NAND gate we achieved a delay improvement up to 11%. The methodology here proposed can be extended to other CMOS logic gates, including complex gates.

Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations

In nanometer scale CMOS parameter variations are a challenge for the design of high yield integrated circuits. This work presents an accurate and computer efficient methodology for statistical modeling of circuit blocks. The model handles co-variances between parameters and supports WD and D2D variations. Using numerical error propagation techniques, it computes the statistical parameters that can be applied at higher level analysis tools, as for instance statistical timing analysis tools. Moreover, we develop a methodology to compute the sensitivity of the circuit output variance to each random variable. This method can be employed by the designer or by an automatic tool in order to improve circuit yield. The methodology for yield analysis proposed in this work is shown to be a solid alternative to traditional Monte Carlo analysis, reducing by orders of magnitude the number of electrical simulations required to characterize memory cells, logic gates and small combinational blocks at electric level. As a case study, we model the yield loss of a SRAM memory due to variability in access time considering variance in threshold voltage and channel width. The results obtained using the proposed model are compared with statistical results obtained by Monte Carlo simulation. A speedup of 70times is achieved, with errorless than 1%

Statistical and Numerical Approach for a Computer efficient circuit yield analysis

In nanometer scale CMOS parameter variations are a challenge for the design of high yield integrated circuits. Statistical Timing Analysis techniques require statistical modeling of logic blocks in the netlist in order to compute mean and standard deviate for system performance. In this work we propose an accurate and computer efficient methodology for statistical modeling of circuit blocks. Numerical error propagation techniques are applied to model within-die and die-todie process variations at electrical level. The model handles co-variances between parameters and spatial correlation, and gives as output the statistical parameters that can be applied at higher level analysis tools, as for instance statistical timing analysis tools. Moreover, we develop a methodology to compute the quantitative contribution of each circuit random parameter to the circuit performance variance. This methodology can be employed by the designer or by an automatic tool in order to improve circuit yield. The methodology for yield analysis proposed in this work is shown to be a solid alternative to traditional Monte Carlo analysis, reducing by orders of magnitude the number of electrical simulations required to analyze memory cells, logic gates and small combinational blocks at electrical level. As a case study, we model the yield loss of a SRAM memory due to variability in access time, considering variance in threshold voltage, channel width and length, which may present both dieto-die and within-die variations. We compare results obtained using the proposed method with statistical results obtained by Monte Carlo simulation. A speedup of 1000× is achieved, with mean error of the standard deviate being 7% compared to MC.

Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas

Em tecnologias nanometricas, variacoes nos parâmetros CMOS sao um desafio para o projeto de circuitos com yield apropriado. Neste trabalho nos propomos uma metodologia eficiente e precisa para a modelagem estatistica de circuitos. Propagacao de erros e tecnicas numericas sao aplicadas para a modelagem em nivel eletrico de variacoes aleatorias e sistematicas durante o processo de fabricacao. O modelo considera covariâncias entre os parâmetros e correlacao espacial, e tem como saida os estimadores estatisticos que podem ser usados em ferramentas de mais alto nivel, tais como ferramentas de analise estatistica de atraso (SSTA). Alem disso, desenvolvemos uma metodologia para a analise quantitativa da contribuicao de cada parâmetro para a variância da resposta do circuito. Como estudos de caso, modelamos o yield de uma memoria SRAM e uma porta NOR dinâmica de pre-carga. No primeiro, consideramos o impacto do comprimento do canal e da tensao de limiar no tempo de acesso da celula de memoria SRAM. Nos desenvolvemos um modelo probabilistico para o atraso de uma NOR dinâmica com keeperb estatico, considerando variacoes na largura do canal e na tensao de limiar. Comparamos os resultados calculados pela metodologia proposta com dados estatistico obtidos a partir de simulacoes Monte Carlo. Reportamos ganho de desempenho de 70×, com um erro menor que 1%.

Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level

In deep-sub-micron technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis. This paper proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study yield of a dynamic-NOR using static keeper. The analytical formulations can be extended to a wide range of dynamic gates (for example pre-charge dynamic gates using dynamic keeper) because we use numerical approach for the calculation of derivatives required by error propagation. The proposed methodology presents errors less than 2% as compared to Monte Carlo simulation, while increasing computational efficiency up to 50×.