Gilson Inacio Wirth

Using Bulk Built-in Current Sensors to Detect Soft Errors

Connecting a built-in current sensor in the design bulk of a digital system increases sensitivity for detecting transient upsets in combinational and sequential logic. SPICE simulations validate this approach and show only minor penalties in terms of area, performance, and power consumption

Statistical Model for MOSFET Bias Temperature Instability Component Due to Charge Trapping

Bias temperature instability (BTI) is a serious reliability concern for MOS transistors. This paper covers theoretical analysis, Monte Carlo simulation, and experimental investigation of the charge trapping component of BTI. An analytical model for both stress and recovery phases of BTI is presented. Furthermore, the model properly describes device behavior under periodic switching, also called AC-BTI or cyclostationary operation. The model is based on microscopic device physics parameters, which are shown to cause statistical variation in transistor BTI behavior. It is shown that a universal logarithmic law describes the time dependence of charge trapping in both stress and recovery phases, and that the time dependence may be separated from the temperature and bias point dependence. Analytical equations for the statistical parameters are provided. The model is compared with experimental data and Monte Carlo simulation results.

Modeling of statistical low-frequency noise of deep-submicrometer MOSFETs

The low-frequency noise (LF-noise) of deep-submicrometer MOSFETs is experimentally studied with special emphasis on yield relevant parameter scattering. A novel modeling approach is developed which includes detailed consideration of statistical effects. The model is based on device physics parameters which cause statistical variations in LF-noise behavior of individual devices. Discrete quantities are used and analytical results for the statistical parameters are derived. Analytical equations for average value and standard deviation of noise power are provided. The model is compatible with standard compact models used for circuit simulation.

Single Event Transients in Logic Circuits—Load and Propagation Induced Pulse Broadening

The generation and propagation of single event transients (SET) in logic gate chains is studied and modeled. Regarding SET generation, we investigate the dependence of the generated SET pulse width on the struck node capacitance. Rising node capacitance may lead to amplified pulse width, indicating that increasing load capacitance alone is not an option for radiation hardening. SET propagation in logic chains is also studied, and it is shown that significant broadening or attenuation of the propagated transient pulse width may be observed. It is shown that the chain design (propagation delay of high to low and low to high transitions) has a major impact on broadening or attenuation of the propagated transient pulse. For the first time a suitable model for SET broadening is provided.

Tbulk-BICS: A Built-In Current Sensor Robust to Process and Temperature Variations for Soft Error Detection

This paper presents a parameterized current sensor able to detect transient ionization in the silicon substrate. Each sensor is controlled by a set of trimming bits that can be used to attune the sensitivity of the sensor compensating process and temperature variations. By choosing different configurations in the trimming bits, it is possible to adjust the performance of the sensor, which can increase the number of transistors monitored by a single sensor reducing the area overhead. Monte Carlo simulations are used to evaluate the sensor behavior. Results from a case-study circuit with embedded Tbulk-BICS confirm the efficiency of the technique.

TID in Flash-Based FPGA: Power Supply-Current Rise and Logic Function Mapping Effects in Propagation-Delay Degradation

We exposed a flash-based FPGA to radiation to measure variations in current, temperature, propagation-delay and duty-cycle in logic circuits. Propagation-delay degradations vary from 400% to 1100% before functional failure, according to circuit and logical mapping. Electrical simulations are carried out to study the difference of behavior in the degradation of different logic mappings.

Characterization and Analysis of the Hysteresis in a ZnO Nanoparticle Thin-Film Transistor

During the past few decades, the interest in flexible and transparent electronics has arisen, and ZnO-based devices present a great potential among these technologies. In this study, ZnO nanoparticles were used to integrate thin-film transistors, whereas cross-linked poly(4-vinylphenol) (PVP) and PECVD-SiO

Design methodology using inversion coefficient for low-voltage low-power CMOS voltage reference

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A Bulk Built-in Current Sensor for SET detection with dynamic memory cell

were used as a gate dielectric layer. Unfortunately, there are reliability concerns in ZnO devices, such as aging and hysteresis. In this study, an experimental investigation of the hysteresis in the transfer characteristic is performed. It was observed that the hysteresis direction is affected by temperature variation when the polymeric dielectric is used. The PVP bulk polarization, the traps in nanoparticles and at the polymeric dielectric interface, as well as the desorption of oxygen molecules in the surface of the nanoparticles, were attributed as the main cause of the hysteretic behavior.

Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits

This paper presents an analog design methodology, using the selection of inversion coefficient of MOS devices, to design low voltage and low-power (LVLP) CMOS voltage references. These circuits often work under subthreshold operation. Hence, there is a demand for analog design methods that optimize the sizing process of transistors working in weak and moderate inversion. The advantage of the presented method -- compared with the traditional approach to design circuits -- is the reduction of design cycle time and minimization of trial-and-error simulations, if the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with supply voltage of 0.7 V was designed for 0.18-¼m CMOS technology.